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參數(shù)資料
| 型號(hào)： | XC4013E-6HG240M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Programmable Gate Arrays |
| 中文描述： | 可編程門陣列 |
| 文件頁數(shù)： | 55/68頁 |
| 文件大?。?/td> | 462K |
| 代理商： | XC4013E-6HG240M |
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R
May 14, 1999 (Version 1.6)
6-59
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Table 23: Pin Functions During Configuration
CONFIGURATION MODE <M2:M1:M0>
SYNCH.
PERIPHERAL
<0:1:1>
M2(LOW) (I)
M1(HIGH) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (I)
RDY/BUSY (O)
SLAVE
SERIAL
<1:1:1>
M2(HIGH) (I)
M1(HIGH) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (I)
MASTER
SERIAL
<0:0:0>
M2(LOW) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (O)
ASYNCH.
PERIPHERAL
<1:0:1>
M2(HIGH) (I)
M1(LOW) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (O)
RDY/BUSY (O)
RS (I)
CS0 (I)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
TCK
TMS
TDO
WS (I)
MASTER
PARALLEL DOWN
<1:1:0>
M2(HIGH) (I)
M1(HIGH) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (O)
RCLK (O)
MASTER
PARALLEL UP
<1:0:0>
M2(HIGH) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (O)
RCLK (O)
USER
OPERATION
(I)
(O)
(I)
I/O
I/O
I/O
DONE
PROGRAM
CCLK (I)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK4-GCK5-I/O
TDI-I/O
TCK-I/O
TMS-I/O
TDO-(O)
I/O
PGCK4-GCK6-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK1-GCK7-I/O
PGCK1-GCK8-I/O
I/O
I/O
I/O
I/O
I/O
ALL OTHERS
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
TCK
TMS
TDO
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
TCK
TMS
TDO
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18*
A19*
A20*
A21*
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
TCK
TMS
TDO
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18*
A19*
A20*
A21*
DIN (I)
DOUT
TDI
TCK
TMS
TDO
DIN (I)
DOUT
TDI
TCK
TMS
TDO
CS1
* XC4000X only
Notes
1. A shaded table cell represents a 50 k
- 100 k
pull-up before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4013E-6HQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-6HQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-6HQ240M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-6MQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-6MQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
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