參數(shù)資料
型號: XC4013E-4PG223C
廠商: Xilinx Inc
文件頁數(shù): 55/68頁
文件大?。?/td> 0K
描述: IC FPGA C-TEMP 5V 4SPD 223-CPGA
產(chǎn)品變化通告: XC4000(E,L) Discontinuation 01/April/2002
標準包裝: 12
系列: XC4000E/X
LAB/CLB數(shù): 576
邏輯元件/單元數(shù): 1368
RAM 位總計: 18432
輸入/輸出數(shù): 192
門數(shù): 13000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 223-BCBGA
供應商設備封裝: 223-CPGA(47.25x47.25)
R
May 14, 1999 (Version 1.6)
6-63
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Figure 55: Master Parallel Mode Programming Switching Characteristics
Address for Byte n
Byte
2 TDRC
Address for Byte n + 1
D7
D6
A0-A17
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
1 TRAC
7 CCLKs
CCLK
3 TRCD
Byte n - 1
X6078
Description
Symbol
Min
Max
Units
RCLK
Delay to Address valid
1
TRAC
0
200
ns
Data setup time
2
TDRC
60
ns
Data hold time
3
TRCD
0ns
Notes:
1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conguration by pulling PROGRAM
Low until Vcc is valid.
2. The rst Data byte is loaded and CCLK starts at the end of the rst RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Product Obsolete or Under Obsolescence
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相關代理商/技術參數(shù)
參數(shù)描述
XC4013E-4PG223I 功能描述:IC FPGA I-TEMP 5V 4SPD 223-CPGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應商設備封裝:900-FCBGA(31x31) 其它名稱:122-1789
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