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參數(shù)資料
| 型號： | XC4013E-4HQ240C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 48/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA C-TEMP 5V 4SPD 240-HQFP |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 576 |
| 邏輯元件/單元數(shù)： | 1368 |
| RAM 位總計： | 18432 |
| 輸入/輸出數(shù)： | 192 |
| 門數(shù)： | 13000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-56
May 14, 1999 (Version 1.6)
Readback Options
Readback options are: Read Capture, Read Abort, and
Clock Select. They are set with the bitstream generation
software.
Read Capture
When the Read Capture option is selected, the readback
data stream includes sampled values of CLB and IOB sig-
nals. The rising edge of RDBK.TRIG latches the inverted
values of the four CLB outputs, the IOB output ip-ops and
the input signals I1 and I2. Note that while the bits describ-
ing conguration (interconnect, function generators, and
RAM content) are
not inverted, the CLB and IOB output sig-
nals
are inverted.
When the Read Capture option is not selected, the values
of the capture bits reect the conguration data originally
written to those memory locations.
If the RAM capability of the CLBs is used, RAM data are
available in readback, since they directly overwrite the F
and G function-table conguration of the CLB.
RDBK.TRIG is located in the lower-left corner of the device,
as shown in Figure 50.
Read Abort
When the Read Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the readback opera-
tion and prepares the logic to accept another trigger.
After an aborted readback, additional clocks (up to one
readback clock per conguration frame) may be required to
re-initialize the control logic. The status of readback is indi-
cated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If readback
must be inhibited for security reasons, the readback control
nets are simply not connected.
RDBK.CLK is located in the lower right chip corner, as
shown in Figure 50.
Violating the Maximum High and Low Time
Specication for the Readback Clock
The readback clock has a maximum High and Low time
specication. In some cases, this specication cannot be
met. For example, if a processor is controlling readback, an
interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specication.
The specication is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the follow-
ing frame. This loading process is dynamic, and is the
source of the maximum High and Low time requirements.
Therefore, the specication only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the rst start bit in the readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the read-
back data relative to the frame. The system must keep track
of the position within a data frame, and disable interrupts
before frame boundaries. Frame lengths and data formats
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the readback feature for bitstream veri-
cation. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-cir-
cuit emulator.
READBACK
DATA
RIP
TRIG
CLK
READ_DATA
OBUF
MD1
MD0
READ_TRIGGER
IBUF
X1786
IF UNCONNECTED,
DEFAULT IS CCLK
Figure 49: Readback Schematic Example
I/O
rdbk
PROGRAMMABLE
INTERCONNECT
rdclk
I/O
X1787
TRIG
DATA
RIP
I
Figure 50: READBACK Symbol in Graphical Editor
Product Obsolete or Under Obsolescence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4013E-4HQ240I | 功能描述:IC FPGA I-TEMP 5V 4SPD 240-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4013E-4HQ240M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-4MQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4013E-4MQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Programmable Gate Arrays |
| XC4013E-4MQ240M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
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