參數(shù)資料
型號(hào): XC4008E
廠商: Xilinx, Inc.
英文描述: XC4000E and XC4000X Series Field Programmable Gate Arrays
中文描述: XC4000E和XC4000X系列現(xiàn)場(chǎng)可編程門(mén)陣列
文件頁(yè)數(shù): 4/4頁(yè)
文件大?。?/td> 21K
代理商: XC4008E
4
XC4000E Logic Cell Array Family
A
Speed Grade
-4
-3
-2
Description
Symbol
Min
Max
Min Max
Min Max Units
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
C inputs via H’ to X/Y outputs
T
ILO
T
IHO
T
HHO
2.0
3.6
2.9
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1,F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators.
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
2.6
4.4
1.7
3.3
0.7
ns
ns
ns
ns
ns
Sequential Delays
Clock K to outputs Q
T
CKO
2.4
ns
Set-up Time before Clock K
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
C
IN
input via F'/G'
C
IN
input via F'/G' and H'
T
ICK
T
IHCK
T
HHCK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
2.3
4.0
3.3
1.9
2.6
1.7
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time after Clock K
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
T
CKI
T
CKIH
T
CKHH
T
CKDI
T
CKEC
T
CKR
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
Clock
Clock High time
Clock Low time
T
CH
T
CL
4.0
4.0
ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
T
RPW
T
RIO
4.0
ns
ns
Master Set/Reset*
Width (High or Low)
Delay from Global Set/Reset net to Q
T
MRW
T
MRQ
18.9
ns
ns
14.4
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
*
Timing is based on the XC4005E. For other devices see XACT timing calculator.
相關(guān)PDF資料
PDF描述
XC4010XL XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013E XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4020E XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4020XL XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4025E XC4000E and XC4000X Series Field Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4008E-1PC84C 功能描述:IC FPGA C-TEMP 5V 1SPD 84-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱(chēng):122-1789
XC4008E-1PC84I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
XC4008E-1PG191C 功能描述:IC FPGA C-TEMP 5V 1SPD 191-CPGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱(chēng):122-1789
XC4008E-1PG191I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
XC4008E-1PQ160C 功能描述:IC FPGA C-TEMP 5V 1SPD 160-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列) 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA(31x31) 其它名稱(chēng):122-1789