參數(shù)資料
型號(hào)： XC4006E-3PC84I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 45/68頁(yè)
文件大?。?/td> 0K
描述： IC FPGA I-TEMP 5V 3SPD 84-PLCC
產(chǎn)品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標(biāo)準(zhǔn)包裝： 15
系列： XC4000E/X
LAB/CLB數(shù)： 256
邏輯元件/單元數(shù)： 608
RAM 位總計(jì)： 8192
輸入/輸出數(shù)： 61
門數(shù)： 6000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC
R
May 14, 1999 (Version 1.6)
6-9
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Detailed Functional Description
XC4000 Series devices achieve high speed through
advanced semiconductor technology and improved archi-
tecture. The XC4000E and XC4000X support system clock
rates of up to 80 MHz and internal performance in excess
of 150 MHz. Compared to older Xilinx FPGA families,
XC4000 Series devices are more powerful. They offer
on-chip edge-triggered and dual-port RAM, clock enables
on I/O ip-ops, and wide-input decoders. They are more
versatile in many applications, especially those involving
RAM. Design cycles are faster due to a combination of
increased routing resources and more sophisticated soft-
ware.
Basic Building Blocks
Xilinx user-programmable gate arrays include two major
congurable elements: congurable logic blocks (CLBs)
and input/output blocks (IOBs).
CLBs provide the functional elements for constructing
the user’s logic.
IOBs provide the interface between the package pins
and internal signal lines.
Three other types of circuits are also available:
3-State buffers (TBUFs) driving horizontal longlines are
associated with each CLB.
Wide edge decoders are available around the periphery
of each device.
An on-chip oscillator is provided.
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these cong-
urable elements to the appropriate networks.
The functionality of each circuit block is customized during
conguration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA. Each of these available circuits is described in this
section.
Congurable Logic Blocks (CLBs)
Congurable Logic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in
Figure 1. Two 4-input function generators (F and G) offer
unrestricted versatility. Most combinatorial logic functions
need four or fewer inputs. However, a third function gener-
ator (H) is provided. The H function generator has three
inputs. Either zero, one, or two of these inputs can be the
outputs of F and G; the other input(s) are from outside the
CLB. The CLB can, therefore, implement certain functions
of up to nine variables, like parity check or expand-
able-identity comparison of two sets of four inputs.
Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the stor-
age elements and function generators can also be used
independently. These storage elements can be congured
as ip-ops in both XC4000E and XC4000X devices; in the
XC4000X they can optionally be congured as latches. DIN
can be used as a direct input to either of the two storage
elements. H1 can drive the other through the H function
generator. Function generator outputs can also drive two
outputs independent of the storage element outputs. This
versatility increases logic capacity and simplies routing.
Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to the programmable intercon-
nect resources outside the block.
Function Generators
Four independent inputs are provided to each of two func-
tion generators (F1 - F4 and G1 - G4). These function gen-
erators, with outputs labeled F’ and G’, are each capable of
implementing any arbitrarily dened Boolean function of
four inputs. The function generators are implemented as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
A third function generator, labeled H’, can implement any
Boolean function of its three inputs. Two of these inputs can
optionally be the F’ and G’ functional generator outputs.
Alternatively, one or both of these inputs can come from
outside the CLB (H2, H0). The third input must come from
outside the block (H1).
Signals from the function generators can exit the CLB on
two outputs. F’ or H’ can be connected to the X output. G’ or
H’ can be connected to the Y output.
A CLB can be used to implement any of the following func-
tions:
any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables1
any single function of ve variables
any function of four variables together with some
functions of six variables
some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators signicantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This exibility improves cell usage.
1. When three separate functions are generated, one of the function outputs must be captured in a ip-op internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.
Product Obsolete or Under Obsolescence
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