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參數(shù)資料
| 型號(hào)： | XC4006E-2PC84I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 32/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 5V 2SPD 84-PLCC |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 256 |
| 邏輯元件/單元數(shù)： | 608 |
| RAM 位總計(jì)： | 8192 |
| 輸入/輸出數(shù)： | 61 |
| 門(mén)數(shù)： | 6000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-42
May 14, 1999 (Version 1.6)
Boundary Scan
The ‘bed of nails’ has been the traditional method of testing
electronic assemblies. This approach has become less
appropriate, due to closer pin spacing and more sophisti-
cated assembly methods like surface-mount technology
and multi-layer boards. The IEEE Boundary Scan Standard
1149.1 was developed to facilitate board-level testing of
electronic assemblies. Design and test engineers can
imbed a standard test logic structure in their device to
achieve high fault coverage for I/O and internal logic. This
structure is easily implemented with a four-pin interface on
any boundary scan-compatible IC. IEEE 1149.1-compati-
ble devices may be serial daisy-chained together, con-
nected in parallel, or a combination of the two.
The XC4000 Series implements IEEE 1149.1-compatible
BYPASS, PRELOAD/SAMPLE and EXTEST boundary
scan instructions. When the boundary scan conguration
option is selected, three normal user I/O pins become ded-
icated inputs for these functions. Another user output pin
becomes the dedicated boundary scan output. The details
of how to enable this circuitry are covered later in this sec-
tion.
By exercising these input signals, the user can serially load
commands and data into these devices to control the driv-
ing of their outputs and to examine their inputs. This
method is an improvement over bed-of-nails testing. It
avoids the need to over-drive device outputs, and it reduces
the user interface to four pins. An optional fth pin, a reset
for the control logic, is described in the standard but is not
implemented in Xilinx devices.
The dedicated on-chip logic implementing the IEEE 1149.1
functions includes a 16-state machine, an instruction regis-
ter and a number of data registers. The functional details
can be found in the IEEE 1149.1 specication and are also
discussed in the Xilinx application note XAPP 017: “
Bound-
ary Scan in XC4000 Devices.”
Figure 40 on page 43 shows a simplied block diagram of
the XC4000E Input/Output Block with boundary scan
implemented. XC4000X boundary scan logic is identical.
CS0, CS1,
WS, RS
I
I/O
These four inputs are used in Asynchronous Peripheral mode. The chip is selected
when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe
(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low
on Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —
and drives D0 - D6 High.
In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.
WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write
Strobe overrides. After configuration, these are user-programmable I/O pins.
A0 - A17
O
I/O
During Master Parallel configuration, these 18 output pins address the configuration
EPROM. After configuration, they are user-programmable I/O pins.
A18 - A21
(XC4003XL to
XC4085XL)
O
I/O
During Master Parallel configuration with an XC4000X master, these 4 output pins add
4 more bits to address the configuration EPROM. After configuration, they are user-pro-
grammable I/O pins. (See Master Parallel Configuration section for additional details.)
D0 - D7
I
I/O
During Master Parallel and Peripheral configuration, these eight input pins receive con-
figuration data. After configuration, they are user-programmable I/O pins.
DIN
I
I/O
During Slave Serial or Master Serial configuration, DIN is the serial configuration data
input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is
the D0 input. After configuration, DIN is a user-programmable I/O pin.
DOUT
O
I/O
During configuration in any mode but Express mode, DOUT is the serial configuration
data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes
on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the
DIN input.
In Express modefor XC4000E and XC4000X only, DOUT is the status output that can
drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O Pins
I/O
Weak
Pull-up
I/O
These pins can be configured to be input and/or output after configuration is completed.
Before configuration is completed, these pins have an internal high-value pull-up resis-
tor (25 k
- 100 k) that defines the logic level as High.
Table 16: Pin Descriptions (Continued)
Pin Name
I/O
During
Cong.
I/O
After
Cong.
Pin Description
Product Obsolete or Under Obsolescence
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