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參數(shù)資料
| 型號： | XC4006 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 219K |
| 代理商： | XC4006 |
2-49
Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
Max
Max
Units
Full length, both pull-ups,
inputs from IOB I-pins
T
WAF
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
9.0
8.0
9.0
10.0
11.0
12.0
14.0
19.0
5.0
6.0
7.0
8.0
9.0
11.0
17.0
ns
ns
ns
ns
ns
ns
ns
10.0
11.0
12.0
13.0
15.0
21.0
Full length, both pull-ups
inputs from internal logic
T
WAFL
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
12.0
13.0
14.0
15.0
16.0
18.0
24.0
11.0
12.0
13.0
14.0
15.0
17.0
23.0
7.0
8.0
9.0
10.0
11.0
13.0
20.0
ns
ns
ns
ns
ns
ns
ns
Half length, one pull-up
inputs from IOB I-pins
T
WAO
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
9.0
10.0
11.0
12.0
13.0
15.0
21.0
8.0
9.0
10.0
11.0
12.0
14.0
19.0
6.0
7.0
8.0
9.0
10.0
12.0
18.0
ns
ns
ns
ns
ns
ns
ns
Half length, one pull-up
inputs from internal logic
T
WAOL
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
12.0
13.0
14.0
15.0
16.0
18.0
24.0
11.0
12.0
13.0
14.0
15.0
17.0
23.0
8.0
9.0
10.0
11.0
12.0
14.0
21.0
ns
ns
ns
ns
ns
ns
ns
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (T
PID
)
and output delay (T
OPF
or T
OPS
), as listed on page 2-52.
PRELIMINARY
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