May 14, 1999 (Version 1.6)
6-5
6
XC4000E and XC4000X Series
Features
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
covers the XC4000XLA and XC4000XV families. Electrical
Specications and package/pin information are covered in
separate sections for each family to make the information
easier to access, review, and print. For access to these sec-
tions, see the Xilinx web site at
System featured Field-Programmable Gate Arrays
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SelectRAMTM memory: on-chip ultra-fast RAM with
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synchronous write option
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dual-port RAM option
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Fully PCI compliant (speed grades -2 and faster)
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Abundant ip-ops
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Flexible function generators
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Dedicated high-speed carry logic
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Wide edge decoders on each edge
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Hierarchy of interconnect lines
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Internal 3-state bus capability
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Eight global low-skew clock or signal distribution
networks
System Performance beyond 80 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
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IEEE 1149.1-compatible boundary scan logic
support
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Individually programmable output slew rate
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Programmable input pull-up or pull-down resistors
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12 mA sink current per XC4000E output
Congured by Loading Binary File
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Unlimited re-programmability
Read Back Capability
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Program verication
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Internal node observability
Backward Compatible with XC4000 Devices
Development System runs on most common computer
platforms
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Interfaces to popular design environments
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Fully automatic mapping, placement and routing
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Interactive design editor for design optimization
Low-Voltage Versions Available
Low-Voltage Devices Function at 3.0 - 3.6 Volts
XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
Additional XC4000X Series Features
High Performance — 3.3 V XC4000XL
High Capacity — Over 180,000 Usable Gates
5 V tolerant I/Os on XC4000XL
0.35
m SRAM process for XC4000XL
Additional Routing Over XC4000E
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almost twice the routing capacity for high-density
designs
Buffered Interconnect for Maximum Speed Blocks
Improved VersaRingTM I/O Interconnect for Better Fixed
Pinout Flexibility
12 mA Sink Current Per XC4000X Output
Flexible New High-Speed Clock Network
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Eight additional Early Buffers for shorter clock delays
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Virtually unlimited number of clock signals
Optional Multiplexer or 2-input Function Generator on
Device Outputs
Four Additional Address Bits in Master Parallel
Conguration Mode
Introduction
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benets of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
The XC4000E and XC4000X Series currently have 20
0
XC4000E and XC4000X Series Field
Programmable Gate Arrays
May 14, 1999 (Version 1.6)
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Product Specification
R
Product Obsolete or Under Obsolescence