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參數(shù)資料
| 型號(hào)： | XC4003E-4PC84I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| 中文描述： | FPGA, 100 CLBS, 2000 GATES, 111 MHz, PQCC84 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 75K |
| 代理商： | XC4003E-4PC84I |
R
February 11, 2000 (Version 1.8)
6-113
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data,
reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted.
Speed Grade
-4
-3
-2
-1
Units
Description
Symbol
Device
Min
Max
Min
Max
Min
Max
Min
Max
Propagation Delays (TTL Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent
latch, no delay
with delay
TPID
TPLI
TPDLI
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
3.0
4.8
10.4
10.8
11.0
11.4
13.8
2.5
3.6
9.3
9.6
10.2
10.6
10.8
11.2
12.4
13.7
2.0
3.6
6.9
7.4
8.1
8.2
8.3
9.8
11.5
12.4
1.4
2.8
6.4
6.5
6.9
7.0
7.3
8.4
9.0
–
ns
Propagation Delays (CMOS Inputs)
Pad to I1, I2
Pad to I1, I2 via transparent
latch, no delay
with delay
TPIDC
TPLIC
TPDLIC
All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E
5.5
8.8
16.5
16.8
17.3
17.5
18.0
20.8
4.1
6.8
12.4
13.2
13.4
13.8
14.0
14.4
15.6
3.7
6.2
11.0
11.9
12.1
12.4
12.6
13.0
14.0
1.9
3.3
6.9
7.0
7.4
7.8
9.0
9.5
–
ns
Propagation Delays
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2
(latch enable, active Low)
TIKRI
TIKLI
All devices
5.6
6.2
2.8
4.0
2.8
3.9
2.7
3.2
ns
Hold Times (Note 1)
Pad to Clock (IK), no delay
with delay
Clock Enable (EC) to Clock (IK),
no delay
with delay
TIKPI
TIKPID
TIKEC
TIKECD
All devices
0
1.5
0
1.5
0
0.9
0
ns
Note 1: Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the
clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up
(default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.
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