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參數(shù)資料
| 型號(hào)： | XC4003E-3PQ100C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 30/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 100 CLB'S 100-PQFP |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 100 |
| 邏輯元件/單元數(shù)： | 238 |
| RAM 位總計(jì)： | 3200 |
| 輸入/輸出數(shù)： | 77 |
| 門(mén)數(shù)： | 3000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-QFP（14x20） |
| 其它名稱(chēng)： | 122-1087 |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-40
May 14, 1999 (Version 1.6)
Table 16: Pin Descriptions
Pin Name
I/O
During
Cong.
I/O
After
Cong.
Pin Description
Permanently Dedicated Pins
VCC
I
Eight or more (depending on package) connections to the nominal +5 V supply voltage
(+3.3 V for low-voltage devices). All must be connected, and each must be decoupled
with a 0.01 - 0.1
F capacitor to Ground.
GND
I
Eight or more (depending on package type) connections to Ground. All must be con-
nected.
CCLK
I or O
I
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheral
mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the
Readback Clock. There is no CCLK High or Low time restriction on XC4000 Series de-
vices, except during Readback. See “Violating the Maximum High and Low Time Spec-
ification for the Readback Clock” on page 56 for an explanation of this exception.
DONE
I/O
O
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on DONE
can be configured to delay the global logic initialization and the enabling of outputs.
The optional pull-up resistor is selected as an option in the XACT
step program that cre-
ates the configuration bitstream. The resistor is included by default.
PROGRAM
I
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to Vcc.
User I/O Pins That Can Have Special Functions
RDY/BUSY
O
I/O
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
RCLK
O
I/O
During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for
XC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK is
useful for clocked PROMs. It is rarely used during configuration. After configuration,
RCLK is a user-programmable I/O pin.
M0, M1, M2
I
I (M0),
O (M1),
I (M2)
As Mode inputs, these pins are sampled after INIT goes High to determine the configu-
ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1
can be used as a 3-state output. These three pins have no associated input or output
registers.
During configuration, these pins have weak pull-up resistors. For the most popular con-
figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three
mode inputs can be individually configured with or without weak pull-up or pull-down re-
sistors. A pull-down resistor value of 4.7 k
is recommended.
These pins can only be used as inputs or outputs when called out by special schematic
definitions. To use these pins, place the library components MD0, MD1, and MD2 in-
stead of the usual pad symbols. Input or output buffers must still be used.
TDO
O
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TDO instead of the usual pad symbol. An out-
put buffer must still be used.
Product Obsolete or Under Obsolescence
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| XC4003E-3PQ100I | 功能描述:IC FPGA I-TEMP 5V 3-SPD 100-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC4003E-3VQ100C | 功能描述:IC FPGA C-TEMP 5V 3SPD 100-VQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC4003E-3VQ100I | 功能描述:IC FPGA I-TEMP 5V 3SPD 100-VQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC4003E4PC84C | 制造商:XILINX 功能描述:* |
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