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參數(shù)資料
| 型號(hào)： | XC4000E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| 中文描述： | XC4000E和XC4000X系列現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 21K |
| 代理商： | XC4000E |
4
XC4000E Logic Cell Array Family
A
Speed Grade
-4
-3
-2
Description
Symbol
Min
Max
Min Max
Min Max Units
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
C inputs via H’ to X/Y outputs
T
ILO
T
IHO
T
HHO
2.0
3.6
2.9
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1,F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators.
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
2.6
4.4
1.7
3.3
0.7
ns
ns
ns
ns
ns
Sequential Delays
Clock K to outputs Q
T
CKO
2.4
ns
Set-up Time before Clock K
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
C
IN
input via F'/G'
C
IN
input via F'/G' and H'
T
ICK
T
IHCK
T
HHCK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
2.3
4.0
3.3
1.9
2.6
1.7
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time after Clock K
F/G inputs
F/G inputs via H’
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
T
CKI
T
CKIH
T
CKHH
T
CKDI
T
CKEC
T
CKR
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
Clock
Clock High time
Clock Low time
T
CH
T
CL
4.0
4.0
ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
T
RPW
T
RIO
4.0
ns
ns
Master Set/Reset*
Width (High or Low)
Delay from Global Set/Reset net to Q
T
MRW
T
MRQ
18.9
ns
ns
14.4
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
*
Timing is based on the XC4005E. For other devices see XACT timing calculator.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4005 | Logic Cell Array Family |
| XC4005H | Logic Cell Array Families |
| XC4010 | Logic Cell Array Family |
| XC4010D | Logic Cell Array Family |
| XC4020 | Logic Cell Array Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4000ESERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Gate Arrays |
| XC4000FM | 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families |
| XC4000H | 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families |
| XC4000XL | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000XLA/XV Field Programmable Gate Arrays |
| XC4000XLA | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000XLA/XV Field Programmable Gate Arrays |
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