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參數(shù)資料
| 型號(hào)： | XC3142A-2PQ100I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 144 CLBS, 2000 GATES, 323 MHz, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 24/50頁 |
| 文件大?。?/td> | 474K |
| 代理商： | XC3142A-2PQ100I |
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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-126
Master Parallel Mode
Figure 22.
Master Parallel Mode
X3159
RCLK
General-
Purpose
User I/O
Pins
M0 M1PWRDWN
M2
HDC
Other
I/O Pins
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
+5 V
.
CE
OE
LCA
Master
CCLK
DOUT
System Reset
A11
A12
A13
A14
A15
EPROM
RESET
.
Other
I/O Pins
DOUT
M2
HDC
LDC
LCA
Slave #1
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
Reset
DOUT
LCA
Slave #n
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
General-
Purpose
User I/O
Pins
RESET
...
+5 V
8
INIT
.
M2
HDC
LDC
INIT
General-
Purpose
User I/O
Pins
+5 V
D/P
Other
I/O Pins
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
Open
Collector
INITN.C.
Reprogram
5 k‰
5 k‰
5 k‰
5 k‰ Each
If Readback is
Activated, a
5-k‰ Resistor is
Required in
Series With M1
*
*
*
*
internal delay of 1.5 CCLK periods, after the rising CCLK
edge that accepts a byte of data, and also changes the
EPROM address, until the falling CCLK edge that makes
the LSB (D0) of this byte appear at DOUT. This means that
DOUT changes on the falling CCLK edge, and the next
LCA device in the daisy chain accepts data on the subse-
quent rising CCLK edge.
In Master Parallel mode, the lead LCA device directly
addresses an industry-standard byte-wide EPROM and
accepts eight data bits right before incrementing (or
decrementing) the address outputs.
The eight data bits are serialized in the lead LCA device,
which then presents the preamble data (and all data that
overflows the lead device) on the DOUT pin. There is an
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