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參數(shù)資料
| 型號(hào)： | XC3142A-09TQ144C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 144 CLBS, 2000 GATES, 370 MHz, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 25/50頁 |
| 文件大小： | 474K |
| 代理商： | XC3142A-09TQ144C |
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2-127
Master Parallel Mode Programming Switching Characteristics
Description
Symbol
Min
Max
Units
RCLK
To address valid
To data setup
To data hold
RCLK High
RCLK Low
1
2
3
T
RAC
T
DRC
T
RCD
T
RCH
T
RCL
0
200
ns
ns
ns
ns
μ
s
60
0
600
4.0
Notes: 1. At power-up, V
CC
must rise from 2.0 V to V
CC
min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V
CC
has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
rise time of
>100 ms, or a non-monotonically rising V
CC
may require a >6-
μ
s High level on RESET, followed by a >6-
μ
s Low
level on RESET and D/P after V
CC
has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode
devices is High.
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Address for Byte n
Byte
2 T
DRC
Address for Byte n + 1
D7
D6
A0-A15
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
1 T
RAC
7 CCLKs
CCLK
3 T
RCD
Byte n - 1
X5380
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3142A-09VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3142A-1PC84C | 制造商:Xilinx 功能描述: |
| XC3142A-1PQ100C | 制造商:Xilinx 功能描述: |
| XC3142A-1TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3142A-1VQ100C | 制造商:Xilinx 功能描述: |
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