參數(shù)資料
型號(hào)： XC3064A-7PQ160C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 29/76頁(yè)
文件大?。?/td> 0K
描述： IC LOGIC CL ARRAY 6400GAT 160PQF
產(chǎn)品變化通告： Product Discontinuation 27/Apr/2010
標(biāo)準(zhǔn)包裝： 1
系列： XC3000A/L
LAB/CLB數(shù)： 224
RAM 位總計(jì)： 46064
輸入/輸出數(shù)： 120
門(mén)數(shù)： 4500
電源電壓： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
其它名稱(chēng)： 122-1030
R
November 9, 1998 (Version 3.1)
7-37
XC3000 Series Field Programmable Gate Arrays
7
Dynamic Power Consumption
Power Consumption
The Field Programmable Gate Array exhibits the low power
consumption characteristic of CMOS ICs. For any design,
the configuration option of TTL chip input threshold
requires power for the threshold reference. The power
required by the static memory cells that hold the configura-
tion data is very low and may be maintained in a
power-down mode.
Typically, most of power dissipation is produced by external
capacitive loads on the output buffers. This load and fre-
quency dependent power is 25
W/pF/MHz per output.
Another component of I/O power is the external dc loading
on all output pins.
Internal power dissipation is a function of the number and
size of the nodes, and the frequency at which they change.
In an FPGA, the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a long
binary counter, the total activity of all counter flip-flops is
equivalent to that of only two CLB outputs toggling at the
clock frequency. Typical global clock-buffer power is
between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz
for the XC3090A. The internal capacitive load is more a
function of interconnect than fan-out. With a typical load of
three general interconnect segments, each CLB output
requires about 0.25 mW per MHz of its output frequency.
Because the control storage of the FPGA is CMOS static
memory, its cells require a very low standby current for data
retention. In some systems, this low data retention current
characteristic can be used as a method of preserving con-
figurations in the event of a primary power loss. The FPGA
has built in powerdown logic which, when activated, will
disable normal operation of the device and retain only the
configuration data. All internal operation is suspended and
output buffers are placed in their high-impedance state with
no pull-ups. Different from the XC3000 family which can be
powered down to a current consumption of a few micro-
amps, the XC3100A draws 5 mA, even in power-down.
This makes power-down operation less meaningful. In con-
trast, ICCPD for the XC3000L is only 10 A.
To force the FPGA into the Powerdown state, the user must
pull the PWRDWN pin Low and continue to supply a reten-
tion voltage to the VCC pins. When normal power is
restored, VCC is elevated to its normal operating voltage
and PWRDWN is returned to a High. The FPGA resumes
operation with the same internal sequence that occurs at
the conclusion of configuration. Internal-I/O and logic-block
storage elements will be reset, the outputs will become
enabled and the DONE/PROG pin will be released.
When VCC is shut down or disconnected, some power
might unintentionally be supplied from an incoming signal
driving an I/O pin. The conventional electrostatic input pro-
tection is implemented with diodes to the supply and
ground. A positive voltage applied to an input (or output)
will cause the positive protection diode to conduct and drive
the VCC connection. This condition can produce invalid
power conditions and should be avoided. A large series
resistor might be used to limit the current or a bipolar buffer
may be used to isolate the input signal.
XC3042A
XC3042L
XC3142A
One CLB driving three local interconnects
0.25
0.17
0.25
mW per MHz
One global clock buffer and clock line
2.25
1.40
1.70
mW per MHz
One device output with a 50 pF load
1.25
mW per MHz
Product Obsolete or Under Obsolescence
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