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參數(shù)資料
| 型號(hào)： | XC2V6000-5FFG1517I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 257/318頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX-II 6M 1517-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-II |
| LAB/CLB數(shù)： | 8448 |
| RAM 位總計(jì)： | 2654208 |
| 輸入/輸出數(shù)： | 1104 |
| 門(mén)數(shù)： | 6000000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1517-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1517-FCBGA（40x40） |
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Virtex-II Platform FPGAs: Functional Description
R
DS031-2 (v3.5) November 5, 2007
Module 2 of 4
Product Specification
35
The Virtex-II implementation process is comprised of Syn-
thesis, translation, mapping, place and route, and configu-
ration file generation. While the tools can be run individually,
many designers choose to run the entire implementation
process with the click of a button. To assist those who prefer
to script their design flows, Xilinx provides Xflow, an auto-
mated single command line process.
Design Verification
In addition to conventional design verification using static
timing analysis or simulation techniques, Xilinx offers pow-
erful in-circuit debugging techniques using ChipScope ILA
(Integrated Logic Analysis). The reconfigurable nature of
Xilinx FPGAs means that designs can be verified in real
time without the need for extensive sets of software simula-
tion vectors.
For simulation, the system extracts post-layout timing infor-
mation from the design database, and back-annotates this
information into the netlist for use by the simulator. The back
annotation features a variety of patented Xilinx techniques,
resulting in the industry’s most powerful simulation flows.
Alternatively, timing-critical portions of a design can be ver-
ified using the Xilinx static timing analyzer or a third party
static timing analysis tool like Synopsys Prime Time, by
exporting timing data in the STAMP data format.
For in-circuit debugging, ChipScope ILA enables designers
to analyze the real-time behavior of a device while operating
at full system speeds. Logic analysis commands and cap-
tured data are transferred between the ChipScope software
and ILA cores within the Virtex-II FPGA, using industry
standard JTAG protocols. These JTAG transactions are
driven over an optional download cable (MultiLINX or
JTAG), connecting the Virtex device in the target system to
a PC or workstation.
ChipScope ILA was designed to look and feel like a logic
analyzer, making it easy to begin debugging a design imme-
diately. Modifications to the desired logic analysis can be
downloaded directly into the system in a matter of minutes.
Other Unique Features of Virtex-II Design Flow
Xilinx design flows feature a number of unique capabilities.
Among these are efficient incremental HDL design flows; a
robust capability that is enabled by Xilinx exclusive hierar-
chical floorplanning capabilities. Another powerful design
capability only available in the Xilinx design flow is “Modular
Design”, part of the Xilinx suite of team design tools, which
enables autonomous design, implementation, and verifica-
tion of design modules.
Incremental Synthesis
Xilinx unique hierarchical floorplanning capabilities enable
designers to create a programmable logic design by isolating
design changes within one hierarchical “l(fā)ogic block”, and
perform synthesis, verification and implementation pro-
cesses on that specific logic block. By preserving the logic in
unchanged portions of a design, Xilinx incremental design
makes the high-density design process more efficient.
Xilinx hierarchical floorplanning capabilities can be speci-
fied using the high-level floorplanner or a preferred RTL
floorplanner (see the Xilinx web site for a list of supported
EDA partners). When used in conjunction with one of the
EDA partners’ floorplanners, higher performance results
can be achieved, as many synthesis tools use this more
predictable detailed physical implementation information to
establish more aggressive and accurate timing estimates
when performing their logic optimizations.
Modular Design
Xilinx innovative modular design capabilities take the incre-
mental design process one step further by enabling the
designer to delegate responsibility for completing the
design, synthesis, verification, and implementation of a hier-
archical “l(fā)ogic block” to an arbitrary number of designers -
assigning a specific region within the target FPGA for exclu-
sive use by each of the team members.
This team design capability enables an autonomous
approach to design modules, changing the hand-off point to
the lead designer or integrator from “my module works in
simulation” to “my module works in the FPGA”. This unique
design methodology also leverages the Xilinx hierarchical
floorplanning capabilities and enables the Xilinx (or EDA
partner) floorplanner to manage the efficient implementa-
tion of very high-density FPGAs.
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