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DS031-1 (v3.5) November 5, 2007
Module 1 of 4
Product Specification
1
Summary of Virtex-II Features
Industry First Platform FPGA Solution
IP-Immersion Architecture
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Densities from 40K to 8M system gates
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420 MHz internal clock speed (Advance Data)
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840+ Mb/s I/O (Advance Data)
SelectRAM Memory Hierarchy
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3 Mb of dual-port RAM in 18 Kbit block SelectRAM
resources
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Up to 1.5 Mb of distributed SelectRAM resources
High-Performance Interfaces to External Memory
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DRAM interfaces
SDR / DDR SDRAM
Network FCRAM
Reduced Latency DRAM
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SRAM interfaces
SDR / DDR SRAM
QDR SRAM
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CAM interfaces
Arithmetic Functions
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Dedicated 18-bit x 18-bit multiplier blocks
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Fast look-ahead carry logic chains
Flexible Logic Resources
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Up to 93,184 internal registers / latches with Clock
Enable
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Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
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Wide multiplexers and wide-input function support
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Horizontal cascade chain and sum-of-products
support
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Internal 3-state bussing
High-Performance Clock Management Circuitry
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Up to 12 DCM (Digital Clock Manager) modules
Precise clock de-skew
Flexible frequency synthesis
High-resolution phase shifting
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16 global clock multiplexer buffers
Active Interconnect Technology
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Fourth generation segmented routing structure
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Predictable, fast routing delay, independent of
fanout
SelectIO-Ultra Technology
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Up to 1,108 user I/Os
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19 single-ended and six differential standards
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Programmable sink current (2 mA to 24 mA) per I/O
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Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
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PCI-X compatible (133 MHz and 66 MHz) at 3.3V
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PCI compliant (66 MHz and 33 MHz) at 3.3V
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CardBus compliant (33 MHz) at 3.3V
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Differential Signaling
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
Bus LVDS I/O
Lightning Data Transport (LDT) I/O with current
driver buffers
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
Built-in DDR input and output registers
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Proprietary high-performance SelectLink
Technology
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
Supported by Xilinx Foundation and Alliance
Series Development Systems
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Integrated VHDL and Verilog design flows
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Compilation of 10M system gates designs
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Internet Team Design (ITD) tool
SRAM-Based In-System Configuration
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Fast SelectMAP configuration
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Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
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IEEE 1532 support
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Partial reconfiguration
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Unlimited reprogrammability
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Readback capability
0.15 m 8-Layer Metal Process with 0.12 m
High-Speed Transistors
1.5V (VCCINT) Core Power Supply, Dedicated 3.3V
VCCAUX Auxiliary and VCCO I/O Power Supplies
IEEE 1149.1 Compatible Boundary-Scan Logic
Support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Three Standard Fine Pitches (0.80 mm,
1.00 mm, and 1.27 mm)
Wire-Bond BGA Devices Available in Pb-Free
100% Factory Tested
7
Virtex-II Platform FPGAs:
Introduction and Overview
DS031-1 (v3.5) November 5, 2007
Product Specification
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