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參數資料
| 型號： | XC2V40-6FF1517C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-II 1.5V Field-Programmable Gate Arrays |
| 中文描述： | 的Virtex - II 1.5V的現場可編程門陣列 |
| 文件頁數： | 1/7頁 |
| 文件大?。?/td> | 127K |
| 代理商： | XC2V40-6FF1517C |
Advance Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
Summary of Virtex
-II Features
Industry First Platform FPGA Solution
IP-Immersion Architecture
-
Densities from 40K to 8M system gates
-
420 MHz internal clock speed (Advance Data)
-
840+ Mb/s I/O (Advance Data)
SelectRAM Memory Hierarchy
-
3 Mb of True Dual-Port RAM in 18-Kbit block
SelectRAM resources
-
Up to 1.5 Mb of distributed SelectRAM
resources
-
High-performance interfaces to external memory
·
DDR-SDRAM interface
·
FCRAM interface
·
QDR
-SRAM interface
·
Sigma RAM interface
Arithmetic Functions
-
Dedicated 18-bit x 18-bit multiplier blocks
-
Fast look-ahead carry logic chains
Flexible Logic Resources
-
Up to 93,184 internal registers / latches with Clock
Enable
-
Up to 93,184 look-up tables (LUTs) or cascadable
16-bit shift registers
-
Wide multiplexers and wide-input function support
-
Horizontal cascade chain and Sum-of-Products
support
-
Internal 3-state bussing
High-Performance Clock Management Circuitry
-
Up to 12 DCM (Digital Clock Manager) modules
·
Precise clock de-skew
·
Flexible frequency synthesis
·
High-resolution phase shifting
-
16 global clock multiplexer buffers
Active Interconnect
Technology
-
Fourth generation segmented routing structure
-
Predictable, fast routing delay, independent of
fanout
SelectI/O-Ultra
Technology
-
Up to 1,108 user I/Os
-
19 single-ended standards and six differential
standards
-
Programmable sink current (2 mA to 24 mA) per I/O
-
Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz
compliance, and CardBus compliant
Differential Signaling
·
840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
·
Bus LVDS I/O
·
Lightning Data Transport (LDT) I/O with current
driver buffers
·
Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
·
Built-in DDR Input and Output registers
Proprietary high-performance SelectLink
Technology
·
High-bandwidth data path
·
Double Data Rate (DDR) link
·
Web-based HDL generation methodology
Supported by Xilinx Foundation
and Alliance
Series Development Systems
-
Integrated VHDL and Verilog design flows
-
Compilation of 10M system gates designs
-
Internet Team Design (ITD) tool
SRAM-Based In-System Configuration
-
Fast SelectMAP
configuration
-
Triple Data Encryption Standard (DES) security
option (Bitstream Encryption)
-
IEEE1532 support
-
Partial reconfiguration
-
Unlimited re-programmability
-
Readback capability
0.15 μm 8-Layer Metal process with 0.12 μm
high-speed transistors
1.5 V (V
CCINT
) core power supply, dedicated 3.3 V
V
CCAUX
auxiliary and V
CCO
I/O power supplies
IEEE 1149.1 compatible boundary-scan logic support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
packages in three standard fine pitches (0.80mm,
1.00mm, and 1.27mm)
100% factory tested
-
-
-
0
Virtex-II 1.5V
Field-Programmable Gate Arrays
DS031-1 (v1.7) October 2, 2001
0
0
Advance Product Specification
R
相關PDF資料 |
PDF描述 |
|---|---|
| XC2V40-6FF1517I | Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V40-6FF896I | Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V2000-6FG676C | Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V40-6FG256C | Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V40-6FG256I | Virtex-II 1.5V Field-Programmable Gate Arrays |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XC2V40-6FF1517I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V40-6FF896C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V40-6FF896I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-II 1.5V Field-Programmable Gate Arrays |
| XC2V40-6FG256C | 制造商:Xilinx 功能描述:FPGA VIRTEX-II 40K GATES 576 CELLS 820MHZ 0.15UM/0.12UM 1.5V - Trays |
| XC2V40-6FG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-II Platform FPGAs: Complete Data Sheet |
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