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參數(shù)資料
| 型號： | XC2S50-6FG256C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 4/99頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 2.5V C-TEMP 256-FBGA |
| 標準包裝： | 90 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 384 |
| 邏輯元件/單元數(shù)： | 1728 |
| RAM 位總計： | 32768 |
| 輸入/輸出數(shù)： | 176 |
| 門數(shù)： | 50000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-FBGA（17x17） |
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Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
12
R
Local Routing
The local routing resources, as shown in Figure 6, provide
the following three types of connections:
Interconnections among the LUTs, flip-flops, and
General Routing Matrix (GRM)
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM
General Purpose Routing
Most Spartan-II FPGA signals are routed on the general
purpose routing, and consequently, the majority of
interconnect resources are associated with this level of the
routing hierarchy. The general routing resources are
located in horizontal and vertical routing channels
associated with the rows and columns CLBs. The
general-purpose routing resources are listed below.
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
96 buffered Hex lines route GRM signals to other
GRMs six blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
may be driven only at their endpoints. Hex-line signals
can be accessed either at the endpoints or at the
midpoint (three blocks from the source). One third of
the Hex lines are bidirectional, while the remaining
ones are unidirectional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
I/O Routing
Spartan-II devices have additional routing resources
around their periphery that form an interface between the
CLB array and the IOBs. This additional routing, called the
VersaRing, facilitates pin-swapping and pin-locking, such
that logic redesigns can adapt to existing PCB layouts.
Time-to-market is reduced, since PCBs and other system
components can be manufactured while the logic design is
still in progress.
Dedicated Routing
Some classes of signal require dedicated routing resources
to maximize performance. In the Spartan-II architecture,
dedicated routing resources are provided for two classes of
signal.
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in Figure 7.
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.
Global Routing
Global Routing resources distribute clocks and other
signals with very high fanout throughout the device.
Spartan-II devices include two tiers of global routing
resources referred to as primary and secondary global
routing resources.
The
primary
global
routing
resources
are
four
dedicated global nets with dedicated input pins that are
designed to distribute high-fanout clock signals with
minimal skew. Each global clock net can drive all CLB,
IOB, and block RAM clock pins. The primary global
nets may only be driven by global buffers. There are
four global buffers, one for each global net.
The secondary global routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These secondary resources
are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
Figure 6: Spartan-II Local Routing
DS001_06_032300
CLB
GRM
To
Adjacent
GRM
To Adjacent
GRM
Direct
Connection
To Adjacent
CLB
To Adjacent
GRM
To Adjacent
GRM
Direct Connection
To Adjacent
CLB
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S50-6FG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S50-6FG456C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S50-6FG456I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S50-6FGG256C | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 50K GATES 1728 CELLS 263MHZ 2.5V 256FBGA - Trays 制造商:Xilinx 功能描述:IC SYSTEM GATE 制造商:Xilinx 功能描述:XC2S50-6FG256C |
| XC2S50-6FGG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
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