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參數(shù)資料
| 型號： | XC2S50-5FG256I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 20/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2.5V I-TEMP 256-FBGA |
| 標準包裝： | 90 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 384 |
| 邏輯元件/單元數(shù)： | 1728 |
| RAM 位總計： | 32768 |
| 輸入/輸出數(shù)： | 176 |
| 門數(shù)： | 50000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-FBGA（17x17） |
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Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
27
R
Design Considerations
This section contains more detailed design information on
the following features:
Delay-Locked Loop . . . see page 27
Block RAM . . . see page 32
Versatile I/O . . . see page 36
Using Delay-Locked Loops
The Spartan-II FPGA family provides up to four fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits that improve and
simplify system level design.
Introduction
Quality on-chip clock distribution is important. Clock skew
and clock delay impact device performance and the task of
managing clock skew and clock delay with conventional
clock trees becomes more difficult in large devices. The
Spartan-II family of devices resolve this potential problem
by providing up to four fully digital dedicated on-chip
Delay-Locked Loop (DLL) circuits which provide zero
propagation delay and low clock skew between output clock
signals distributed throughout the device.
Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network
minimizes clock skews due to loading differences. By
monitoring a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the
individual clock loads within the device.
In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.
Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at
100 MHz. This technique can simplify board design
because the clock path on the board no longer distributes
such a high-speed signal. A multiplied clock also provides
designers the option of time-domain-multiplexing, using one
circuit twice per clock cycle, consuming less area than two
copies of the same circuit.
The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to de-skew a board level clock between multiple devices.
In order to guarantee the system clock establishes prior to
the device "waking up," the DLL can delay the completion of
the device configuration process until after the DLL
achieves lock.
By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance
clocks.
Library DLL Primitives
Figure 22 shows the simplified Xilinx library DLL macro,
BUFGDLL. This macro delivers a quick and efficient way to
provide a system clock with zero propagation delay
two library DLL primitives. These primitives provide access
to the complete set of DLL features when implementing
more complex applications.
Figure 22: Simplified DLL Macro BUFGDLL
Figure 23: Standard DLL Primitive CLKDLL
Figure 24: High-Frequency DLL Primitive CLKDLLHF
0 ns
DS001_22_032300
O
I
CLK0
CLK90
CLK180
CLK270
CLKIN
DS001_23_032300
CLKDLL
RST
CLKFB
CLK2X
CLKDV
LOCKED
CLK0
CLK180
CLKDV
LOCKED
CLKIN
DS001_24_032300
CLKDLLHF
RST
CLKFB
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S50-5FG456C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S50-5FG456I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S50-5FGG256C | 功能描述:IC SPARTAN-II FPGA 50K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| XC2S50-5FGG256I | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 50K GATES 1728 CELLS 263MHZ 2.5V 256FBGA - Trays |
| XC2S50-5FGG456C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
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