參數(shù)資料
型號： XC2S150-5FGG456C
廠商： Xilinx Inc
文件頁數(shù)： 25/99頁
文件大小： 0K
描述： IC SPARTAN-II FPGA 150K 456-FBGA
標準包裝： 60
系列： Spartan®-II
LAB/CLB數(shù)： 864
邏輯元件/單元數(shù)： 3888
RAM 位總計： 49152
輸入/輸出數(shù)： 260
門數(shù)： 150000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 456-BBGA
供應(yīng)商設(shè)備封裝： 456-FBGA
其它名稱： 122-1307
Spartan-II FPGA Family: Functional Description
DS001-2 (v2.8) June 13, 2008
Module 2 of 4
Product Specification
31
R
Useful Application Examples
The Spartan-II FPGA DLL can be used in a variety of
creative and useful applications. The following examples
show some of the more common applications.
Standard Usage
The circuit shown in Figure 28 resembles the BUFGDLL
macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.
Deskew of Clock and Its 2x Multiple
The circuit shown in Figure 29 implements a 2x clock
multiplier and also uses the CLK0 clock output with zero ns
skew between registers on the same chip. A clock divider
circuit could alternatively be implemented using similar
connections.
Because any single DLL can only access at most two
BUFGs, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
Generating a 4x Clock
By connecting two DLL circuits each implementing a 2x
clock multiplier in series as shown in Figure 30, a 4x clock
multiply can be implemented with zero skew between
registers in the same device.
If other clock output is needed, the clock could access a
BUFG only if the DLLs are constrained to exist on opposite
edges (Top or Bottom) of the device.
When using this circuit it is vital to use the SRL16 cell to
reset the second DLL after the initial chip reset. If this is not
done, the second DLL may not recognize the change of
frequencies from when the input changes from a 1x (25/75)
waveform to a 2x (50/50) waveform. It is not recommended
to cascade more than two DLLs.
For design examples and more information on using the
DLL, see XAPP174, Using Delay-Locked Loops in Spartan-II
FPGAs.
Figure 28: Standard DLL Implementation
Figure 29: DLL Deskew of Clock and 2x Multiple
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLKIN
CLKFB
RST
DS001_28_061200
CLKDLL
BUFG
IBUFG
OBUF
IBUF
CLK0
CLK90
CLK180
CLK270
CLK2X
CLKDV
LOCKED
CLKIN
CLKFB
RST
DS001_29_061200
CLKDLL
BUFG
IBUFG
OBUF
BUFG
IBUF
Figure 30: DLL Generation of 4x Clock
DS001_30_061200
RST
CLKFB
CLKIN
CLKDLL
LOCKED
CLKDV
INV
BUFG
OBUF
SRL16
D
A3
A2
A1
A0
WCLK
BUFG
Q
IBUFG
CLK2X
CLK0
CLK90
CLK180
CLK270
RST
CLKFB
CLKIN
CLKDLL
LOCKED
CLKDV
CLK2X
CLK0
CLK90
CLK180
CLK270
相關(guān)PDF資料
PDF描述
25AA040A-I/MS IC EEPROM 4KBIT 10MHZ 8MSOP
25AA020A-I/P IC EEPROM 2KBIT 10MHZ 8DIP
93C76CT-I/MC IC EEPROM 8KBIT 3MHZ 8DFN
93LC86CT-I/ST IC EEPROM 16KBIT 3MHZ 8TSSOP
93LC86CT-I/MS IC EEPROM 16KBIT 3MHZ 8MSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S150-5FGG456I 制造商:Xilinx 功能描述:FPGA SPARTAN-II 150K GATES 3888 CELLS 263MHZ 2.5V 456FBGA - Trays
XC2S1505PQ208C 制造商:XILINX 功能描述:IC 制造商:XILINX 功能描述:*
XC2S150-5PQ208C 功能描述:IC FPGA 2.5V 864 CLB'S 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S150-5PQ208I 功能描述:IC FPGA 2.5V I-TEMP 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-II 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S150-5PQ208Q 制造商:Xilinx 功能描述:XC2S150-5PQ208Q - Trays 制造商:Xilinx 功能描述:Xilinx XC2S150-5PQ208Q FPGA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*