參數(shù)資料
型號: XC2C64A-7VQG44I
廠商: Xilinx Inc
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC CR-II CPLD 64MCELL 44-VQFP
標(biāo)準(zhǔn)包裝: 160
系列: CoolRunner II
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 6.7ns
電壓電源 - 內(nèi)部: 1.7 V ~ 1.9 V
邏輯元件/邏輯塊數(shù)目: 4
宏單元數(shù): 64
門數(shù): 1500
輸入/輸出數(shù): 33
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-VQFP(10x10)
包裝: 托盤
配用: 122-1536-ND - KIT STARTER SPARTAN-3E
122-1532-ND - KIT DEVELOPMENT SPARTAN 3ADSP
其它名稱: 122-1708
XC2C64A-7VQG44I-ND
CoolRunner-II CPLD Family
10
DS090 (v3.1) September 11, 2008
Product Specification
R
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. See WP170 for more detail.
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
GCK0
GCK1
GCK2
CLK_CT
PTC
DS090_09_121201
D/T
CE
CK
FIF
Latch
DualEDGE
Q
GCK0
GCK1
GCK2
CTC
PTC
D/T
CE
CK
FIF
Latch
DualEDGE
Q
Clock
In
÷2
÷4
÷6
÷8
÷10
÷12
÷14
÷16
GCK2
Synch Reset
Synch Rst
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