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參數(shù)資料
| 型號(hào)： | XC2C512 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | CoolRunner-II CPLD Family |
| 中文描述： | 的CoolRunner - II CPLD系列 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 458K |
| 代理商： | XC2C512 |
2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Optimized for 1.8V systems
-
Industry’s fastest low power CPLD
-
Densities from 32 to 512 macrocells
Industry’s best 0.18 micron CMOS CPLD
-
Optimized architecture for effective logic synthesis
-
Multi-voltage I/O operation — 1.5V to 3.3V
Advanced system features
-
Fastest in system programming
·
1.8V ISP using IEEE 1532 (JTAG) interface
-
On-The-Fly Reconfiguration (OTF)
-
IEEE1149.1 JTAG Boundary Scan Test
-
Optional Schmitt trigger input (per pin)
-
Multiple I/O banks on all devices
-
Unsurpassed low power management
·
DataGATE external signal control
-
Flexible clocking modes
·
Optional DualEDGE triggered registers
·
Clock divider (
÷
2,4,6,8,10,12,14,16)
·
CoolCLOCK
-
Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
·
Multiple global output enables
·
Global set/reset
-
Abundant product term clocks, output enables and
set/resets
-
Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
-
Advanced design security
-
Open-drain output option for Wired-OR and LED
drive
-
Optional bus-hold, 3-state or weak pullup on select
I/O pins
-
Optional configurable grounds on unused I/Os
-
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels on all parts
SSTL2_1,SSTL3_1, and HSTL_1 on 128
macrocell and denser devices
Hot pluggable
PLA architecture
-
Superior pinout retention
-
100% product term routability across function block
Wide package availability including fine pitch:
-
Chip Scale Package (CSP) BGA, Fine Line BGA,
TQFP, PQFP, VQFP, PLCC, and QFN packages
-
Pb-free available for all packages
Design entry/verification using Xilinx and industry
standard CAE tools
Free software support for all densities using Xilinx
WebPACK
Industry leading nonvolatile 0.18 micron CMOS
process
-
Guaranteed 1,000 program/erase cycles
-
Guaranteed 20 year data retention
Family Overview
Xilinx CoolRunner-II CPLDs deliver the high speed and
ease of use associated with the XC9500/XL/XV CPLD fam-
ily with the extremely low power versatility of the XPLA3
family in a single CPLD. This means that the exact same
parts can be used for high-speed data communications/
computing systems and leading edge portable products,
with the added benefit of In System Programming. Low
power consumption and high-speed operation are com-
bined into a single family that is easy to use and cost effec-
tive. Clocking techniques and other power saving features
extend the users’ power budget. The design features are
supported starting with Xilinx ISE 4.1i ISE WebPACK. Addi-
tional details can be found in
Further Reading
, page 13
.
Table 1
shows the macrocell capacity and key timing
parameters for the CoolRunner-II CPLD family.
-
-
0
CoolRunner-II CPLD Family
DS090 (v2.5) June 28, 2005
0
0
Product Specification
R
Table 1:
CoolRunner-II CPLD Family Parameters
XC2C32A
Macrocells
Max I/O
T
PD
(ns)
T
SU
(ns)
T
CO
(ns)
F
SYSTEM1
(MHz)
XC2C64A
64
64
4.6
2.0
3.9
263
XC2C128
128
100
5.7
2.4
4.2
244
XC2C256
256
184
5.7
2.4
4.5
256
XC2C384
384
240
7.1
2.9
5.8
217
XC2C512
512
270
7.1
2.6
5.8
179
32
33
3.8
1.9
3.7
323
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|---|---|
| XC2C512-10FG324C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 12K GATES 512 MCRCLLS 166MHZ 0.18UM 1.8V - Trays 制造商:Xilinx 功能描述:IC CRII CPLD 512MCRCELL 324BGA 制造商:Xilinx 功能描述:IC CPLD 512MC 9.2NS 324BGA |
| XC2C512-10FG324I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 12K GATES 512 MCRCLLS 166MHZ 0.18UM 1.8V - Trays 制造商:Xilinx 功能描述:IC CRII CPLD 512MCRCELL 324BGA 制造商:Xilinx 功能描述:IC CPLD 512MC 9.2NS 324BGA |
| XC2C512-10FGG324C | 功能描述:IC CRII CPLD 512MCRCELL 324BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:160 系列:ispMACH® 4000V 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.5ns 電壓電源 - 內(nèi)部:3 V ~ 3.6 V 邏輯元件/邏輯塊數(shù)目:2 宏單元數(shù):32 門數(shù):- 輸入/輸出數(shù):30 工作溫度:-40°C ~ 130°C 安裝類型:表面貼裝 封裝/外殼:44-TQFP 供應(yīng)商設(shè)備封裝:44-TQFP（10x10） 包裝:托盤 |
| XC2C512-10FGG324I | 功能描述:IC CR-II CPLD 512MCRCELL 324FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner II 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP（24x24） 包裝:托盤 |
| XC2C512-10FT256C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER-II 12K GATES 512 MCRCLLS 166MHZ COMM 0.18UM - Trays 制造商:Xilinx 功能描述:IC CRII CPLD 512MCRCELL 256BGA 制造商:Xilinx 功能描述:IC CPLD 512MC 9.2NS 256BGA |
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