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參數(shù)資料
| 型號： | XC2C512-10FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 0K |
| 描述： | IC CR-II CPLD 512MCELL 256-FTBGA |
| 標準包裝： | 90 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統(tǒng)內可編程 |
| 最大延遲時間 tpd(1)： | 9.2ns |
| 電壓電源 - 內部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數(shù)目： | 32 |
| 宏單元數(shù)： | 512 |
| 門數(shù)： | 12000 |
| 輸入/輸出數(shù)： | 212 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應商設備封裝： | 256-FTBGA |
| 包裝： | 托盤 |
CoolRunner-II CPLD Family
DS090 (v3.1) September 11, 2008
3
Product Specification
R
CoolRunner-II CPLD I/O standards.)
Architecture Description
CoolRunner-II CPLD is a highly uniform family of fast, low
power CPLDs. The underlying architecture is a traditional
CPLD architecture combining macrocells into Function
Blocks (FBs) interconnected with a global routing matrix,
the Xilinx Advanced Interconnect Matrix (AIM). The FBs use
a Programmable Logic Array (PLA) configuration which
allows all product terms to be routed and shared among any
of the macrocells of the FB. Design software can efficiently
synthesize and optimize logic that is subsequently fit to the
FBs and connected with the ability to utilize a very high per-
centage of device resources. Design changes are easily
and automatically managed by the software, which exploits
the 100% routability of the Programmable Logic Array within
each FB. This extremely robust building block delivers the
industry’s highest pinout retention, under very broad design
conditions. The architecture is explained in more detail with
the discussion of the underlying FBs, logic and intercon-
nect.
The design software automatically manages these device
resources so that users can express their designs using
completely generic constructs without knowledge of these
architectural details. More advanced users can take advan-
tage of these details to more thoroughly understand the
software’s choices and direct its results.
Figure 1 shows the high-level architecture whereby FBs
attach to pins and interconnect to each other within the
internal interconnect matrix. Each FB contains 16 macro-
cells. The BSC path is the JTAG Boundary Scan Control
Table 4: CoolRunner-II CPLD Family Features
XC2C32A
XC2C64A
XC2C128
XC2C256
XC2C384
XC2C512
IEEE 1532
I/O banks
2
4
Clock division
-
DualEDGE
Registers
DataGATE
-
LVTTL
LVCMOS33, 25,
18, and 15(1)
SSTL2_1
-
SSTL3_1
-
HSTL_1
-
Configurable
ground
Quadruple data
security
Open drain outputs
Hot plugging
Schmitt Inputs
1.
LVCMOS15 requires the use of Schmitt-trigger inputs.
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