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參數(shù)資料
| 型號(hào)： | XC18V02 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable Configuration PROMs(在系統(tǒng)可編程配置PROM) |
| 中文描述： | 在系統(tǒng)可編程配置PROM的（在系統(tǒng)可編程配置PROM的） |
| 文件頁數(shù)： | 1/19頁 |
| 文件大小： | 184K |
| 代理商： | XC18V02 |
DS026 (v2.5) November 13, 2000
Product Specification
1-800-255-77781
2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
-
Endurance of 20,000 program/erase cycles
-
Program/erase over full commercial/industrial
voltage and temperature range
IEEE Std 1149.1 boundary-scan (JTAG) support
Simple interface to the FPGA; could be configured to
use only one user I/O pin
Cascadable for storing longer or multiple bitstreams
Dual configuration modes
-
Serial Slow/Fast configuration (up to 33 MHz)
-
Parallel (up to 264 Mbps at 33 MHz)
Low-power advanced CMOS FLASH process
5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals.
3.3V or 2.5V output capability
Available in PC20, SO20, PC44 and VQ44 packages.
Design support using the Xilinx Alliance and
Foundation series software packages.
JTAG command initiation of standard FPGA
configuration.
Description
Xilinx introduces the XC18V00 series of in-system program-
mable configuration PROMs. Initial devices in this 3.3V
family are a 4-megabit, a 2-megabit, a 1-megabit, a
512-Kbit, and a 256-Kbit PROM that provide an
easy-to-use, cost-effective method for re-programming and
storing large Xilinx FPGA or CPLD configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
When the FPGA is in Express or SelectMAP Mode, an
external oscillator will generate the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROMs DATA (D0-D7) pins.
The data will be clocked into the FPGA on the following ris-
ing edge of the CCLK. Neither Express nor SelectMAP uti-
lize a Length Count, so a free-running oscillator may be
used. See
Figure 6
.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC1700L one-time programmable Serial PROM family.
0
XC18V00 Series of In-System
Programmable Configuration
PROMs
Product Specification
DS026 (v2.5) November 13, 2000
0
5
R
Figure 1:
XC18V00 Series Block Diagram
Control
and
JTAG
Interface
Memory
Serial
or
Parallel
Interface
D0 DATA
(Serial or Parallel
[Express/SelectMAP] Mode)
D[1:7]
Express Mode and
SelectMAP Interface
Data
Address
CLK CE
TCK
TMS
TDI
TDO
OE/Reset
CEO
Data
DS026_01_021000
7
CF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC18V02PC20 | 制造商:XILINX 制造商全稱:XILINX 功能描述:In-System Programmable Configuration PROMs |
| XC18V02PC20C | 制造商:XILINX 制造商全稱:XILINX 功能描述:In-System Programmable Configuration PROMs |
| XC18V02PC44 | 制造商:MAJOR 功能描述: |
| XC18V02PC44C | 功能描述:IC PROM SERIAL CONFIG 2M 44-PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲(chǔ)容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| XC18V02-PC44C | 制造商:Xilinx 功能描述:Serial EEPROM, 44 Pin, Plastic, PLCC |
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