R
PROM Pinouts for XC17V04, XC17V02, and
XC17V01
(Pins not listed are
“
no connect
”
)
Capacity
Controlling PROMs
Connecting the FPGA device with the PROM.
The DATA output(s) of the PROM(s) drives the D
IN
input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V
CC
glitch.
The PROM CE input is best connected to the FPGA
DONE pin(s) and a pullup resistor. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
15 mA maximum.
SelectMAP mode is similar to Slave Serial mode. The
DATA is clocked out of the PROM one byte per CCLK
instead of one bit per CCLK cycle. See FPGA data
sheets for special configuration requirements.
Pin Name
8-pi
VOIC
(1)
20-pin
SOIC
(1)
20-pin
PLCC
(1,2)
44-pin
VQFP
(2)
44-pin
PLCC
(2)
DATA
1
1
1
40
2
CLK
2
3
3
43
5
RESET/OE
(OE/RESET)
3
8
8
13
19
CE
4
10
10
15
21
GND
5
11
11
18, 41
24, 3
CEO
6
13
13
21
27
V
PP
7
18
18
35
41
V
CC
8
20
20
38
44
Notes:
1.
2.
XC17V01 available in these packages.
XC17V02 and XC17V04 available in these packages.
Devices
XC17V04
XC17V02
XC17V01
Configuration Bits
4,194,304
2,097,152
1,679,360
Xilinx FPGAs and Compatible PROMs
Device
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
Configuration
Bits
360,160
635,360
1,697,248
2,761,952
4,082,656
5,659,360
7,492,064
10,494,432
15,660,000
21,849, 568
PROM
XC17V01
XC17V01
XC17V02
XC17V04
XC17V04
XC17V08
XC17V08
XC17V16
XC17V16
XC17V16 +
XC17V08
2 of XC17V16
XC17V01
XC17V01
XC17V01
XC17V01
XC17V02
XC2V8000
XCV50
XCV100
XCV150
XCV200
XCV300
29,063,072
559,200
781,216
1,040,096
1,335,840
1,751,808
XCV400
XCV600
XCV800
XCV1000
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV405E
XCV600E
XCV812E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
Notes:
1.
The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
2,546,048
3,607,968
4,715,616
6,127,744
630,048
863,840
1,442,106
1,875,648
2,693,440
3,430,400
3,961,632
6,519,648
6,587,520
8,308,992
10,159,648
12,922,336
16,283,712
XC17V04
XC17V04
XC17V08
XC17V08
XC17V01
XC17V01
XC17V01
XC17V02
XC17V04
XC17V04
XC17V04
XC17V08
XC17V08
XC17V08
XC17V16
XC17V16
XC17V16
Xilinx FPGAs and Compatible PROMs
Configuration
Device
Bits
PROM