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參數(shù)資料
| 型號(hào)： | XC17V01SERIES |
| 英文描述： | XC17V00 Series Configuration PROM |
| 中文描述： | XC17V00系列配置PROM |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 157K |
| 代理商： | XC17V01SERIES |
XC17V00 Series Configuration PROM
DS073 (v1.5) October 9, 2001
Advance Product Specification
1-800-255-77783
R
Pin Description
DATA[0:7]
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the D0 pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
Note:
XC17V04, XC17V02, and XC17V01 have serial output
only.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The polar-
ity of this input pin is programmable as either RESET/OE or
OE/RESET. To avoid confusion, this document describes
the pin as RESET/OE, although the opposite polarity is pos-
sible on all devices. When RESET is active, the address
counter is held at
“
0
”
, and puts the DATA output in a
high-impedance state. The polarity of this input is program-
mable. The default is active High RESET, but the preferred
option is active Low RESET, because it can connected to
the FPGAs INIT pin and a pullup resistor.
The polarity of this pin is controlled in the programmer inter-
face. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have differ-
ent methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I
CC
standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next PROM in the daisy chain. This output is Low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
Low.
BUSY (XC17V16 and XC17V08 only)
If BUSY pin is floating, the user must program the BUSY bit
which will cause BUSY pin to be internally tied to a
pull-down resistor. When asserted High, output data are
held and when BUSY pin goes Low, data output will
resume.
V
PP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read oper-
ation, this pin must be connected to V
CC
. Failure to do so
may lead to unpredictable, temperature-dependent opera-
tion and severe problems in circuit debugging. Do not leave
V
PP
floating!
V
CC
and GND
Positive supply and ground pins.
PROM Pinouts for XC17V16 and XC17V08
(Pins not listed are
“
no connect
”
)
Capacity
Pin Name
44-pin VQFP
44-pin PLCC
BUSY
24
30
D0
40
2
D1
29
35
D2
42
4
D3
27
33
D4
9
15
D5
25
31
D6
14
20
D7
19
25
CLK
43
5
RESET/OE
(OE/RESET)
13
19
CE
15
21
GND
6, 18, 28, 37, 41
3, 12, 24, 34, 43
CEO
21
27
V
PP
V
CC
35
41
8, 16, 17, 26, 36,
38
14, 22, 23, 32,
42, 44
Devices
Configuration Bits
XC17V16
16,777,216
XC17V08
8,388,608
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| XC17V16SERIES | XC17V00 Series Configuration PROM |
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