
DS108-1 (v1.5) September 29, 2005
1
Preliminary Product Specification
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Features
AEC-Q100 device qualification and full PPAP support
available in both extended temperature Q-grade and
I-grade.
Guaranteed to meet full electrical specifications over
TA = –40°C to +125°C (Q-grade)
System frequency up to 100 MHz (10 ns)
Available in small footprint packages
Optimized for high-performance 3.3V systems
-
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals — ideal for multi-voltage system interfacing
and level shifting
-
Technology: 0.35
m CMOS process
Advanced system features
-
In-system programmable enabling higher system
reliability through reduced handling and reducing
production programming times
-
Superior pin-locking and routability with
FastCONNECT II switch matrix allowing for
multiple design iterations without board re-spins
-
Input hysteresis on all user and boundary-scan pin
inputs to reduce noise on input signals
-
Bus-hold circuitry on all user pin inputs which
reduces cost associated with pull-up resistors and
reduces bus loading
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
for in-system device testing
Fast concurrent programming
Slew rate control on individual outputs for reducing EMI
generation
Refer to XC9500XL Family data sheet (DS054) for
architecture description
Refer to XC9536XL data sheet (DS058), the
XC9572XL data sheet (DS057), and the XC95144XL
data sheet (DS056) for pin tables
Xilinx received TS 16949 Certification in March 2005.
Description
The XA9500XL 3.3V CPLD Automotive XA product family is
targeted for leading-edge, high-performance automotive
applications that require either automotive industrial (–40°C
to +85°C ambient) or extended (–40°C to +125°C ambient)
temperature reconfigurable devices.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in the XA9500XL device can be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f
where:
MCHP = Macrocells in high-performance (default)
mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual ICC value varies
with the design application and should be verified during
normal system operation.
0
XA9500XL High-Performance
CPLD Automotive XA Product
Family
DS108-1 (v1.5) September 29, 2005
00
Preliminary Product Specification
R
Table 1: XA9500XL Device Family
Device
Temperature Grade
Macrocells
Usable Gates
Registers
fSYSTEM (MHz)
XA9536XL
I, Q
36
800
36
100
XA9572XL
I, Q
72
1,600
72
100
XA95144XL
I
144
3,200
144
100