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參數(shù)資料
| 型號： | XA3S500E-4FTG256Q |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 30/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN-3E 500K 256FTBGA |
| 標準包裝： | 90 |
| 系列： | Spartan®-3E XA |
| LAB/CLB數(shù)： | 1164 |
| 邏輯元件/單元數(shù)： | 10476 |
| RAM 位總計： | 368640 |
| 輸入/輸出數(shù)： | 190 |
| 門數(shù)： | 500000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
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DS635 (v2.0) September 9, 2009
Product Specification
36
R
Revision History
The following table shows the revision history for this document.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Date
Version
Revision
08/31/07
1.0
Initial Xilinx release.
01/20/09
1.1
Removed Table 45: MultiBoot Trigger Timing.
09/09/09
2.0
Added package sizes to Table 2, page 4.
Removed Genealogy Viewer Link from "Package Marking," page 5.
Updated data and notes for Table 6, page 8.
Updated notes for Table 8, page 9.
Updated Max VCCO for LVTTL and LVCMOS33, removed PCIX data, updated VIL Max for
LVCMOS18, LVCMOS15, and LVCMOS12, updated VIH Min for LVCMOS12, and added
note 6 in Table 9, page 11.
Removed PCIX data, revised note 2, and added note 4 in Table 10, page 12.
Updated figure description of Figure 5, page 14.
Added note 4 to Table 13, page 14.
Removed PC166_3 and PCIX adjustment values from Table 17, page 17.
Deleted Table 18 (duplicate of Table 17, page 17). Subsequent tables renumbered.
Removed PCIX data Table 18, page 18.
Removed PCIX data and removed VREF values for DIFF_HSTL_I_18,
DIFF_HSTL_III_18, DIFF_SSTL18_I, and DIFF_SSTL2_I from Table 19, page 19.
Updated notes, references to notes, and revised the maximum clock-to-output times for
TMSCKP_P Table 24, page 22.
Added "Spread Spectrum," page 24.
Updated note 3 in Table 26, page 25.
Added note 4 Table 28, page 26.
Updated notes, references to notes, and CLKOUT_PER_JITT_FX data in Table 29,
Updated MAX_STEPS data in Table 31, page 28.
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