參數資料
型號: XA3S400-4PQG208Q
廠商: Xilinx Inc
文件頁數: 6/8頁
文件大小: 0K
描述: IC FPGA SPARTAN-3 400K 208-PQFP
標準包裝: 1
系列: Spartan®-3 XA
LAB/CLB數: 896
邏輯元件/單元數: 8064
RAM 位總計: 294912
輸入/輸出數: 141
門數: 400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
Introduction and Ordering Information
DS314 (v1.3) June 18, 2009
Product Specification
6
R
Ordering Information
Spartan-3 FPGAs are available in Pb-free packaging options for all device/package combinations. The Pb-free packages
include a special “G” character in the ordering code.
Table 5: Quiescent Supply Current Characteristics
Symbol
Description
Device
I-Grade
Maximum
Q-Grade
Maximum
Units
ICCINTQ
Quiescent VCCINT supply current
XA3S50
50
100
mA
XA3S200
125
200
mA
XA3S400
180
250
mA
XA3S1000
315
400
mA
XA3S1500
410
-
mA
ICCOQ
Quiescent VCCO supply current
XA3S50
12
mA
XA3S200
12
mA
XA3S400
14
mA
XA3S1000
14
mA
XA3S1500
16
-
mA
ICCAUXQ
Quiescent VCCAUX supply current
XA3S50
22
25
mA
XA3S200
33
35
mA
XA3S400
44
50
mA
XA3S1000
55
60
mA
XA3S1500
85
-
mA
Notes:
1.
The numbers in this table are based on the conditions set forth in Table 31 of DS099. Quiescent supply current is measured with all
I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are
characterized using devices with typical processing at ambient room temperature (TA of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and
VCCAUX = 2.5V). Maximum values are the production test limits measured for each device at the maximum specified junction
temperature and at maximum voltage limits with VCCINT = 1.26V, VCCO = 3.45V, and VCCAUX = 2.625V. The FPGA is programmed
with a “blank” configuration data file (i.e., a design with no functional elements instantiated). For conditions other than those
described above, (e.g., a design including functional elements, the use of DCI standards, etc.), measured quiescent current levels
may be different than the values in the table. Use the XPower Power Estimator for more accurate estimates. See Note 2.
2.
There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
XPower Power Estimator at http://www.xilinx.com/ise/power_tools provides quick, approximate, typical estimates, and does not
require a netlist of the design. b) XPower, part of the Xilinx ISE development software, uses the FPGA netlist as input to provide more
accurate maximum and typical estimates.
3.
The maximum numbers in this table also indicate the minimum current each power rail requires in order for the FPGA to power-on
successfully, once all three rails are supplied. If VCCINT is applied before VCCAUX, there may be temporary additional ICCINT current
until VCCAUX is applied. See Surplus ICCINT if VCCINT Applied before VCCAUX, page 51 of DS099.
Figure 2:
Spartan-3 BGA Package Marking Example for Part Number XA3S1000-4 FTG256Q
Lot Code
Date Code
XA3S1000
TM
4Q
SPARTAN
Device Type
BGA Ball A1
Package
Speed Grade
Temperature Range
R
FTG256EGQ0525
D1234567A
Mask Revision Code
Process Code
Fabrication Code
DS314-1_02_100808
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