參數(shù)資料
型號： X98021L128-3.3-Z
廠商： INTERSIL CORP
元件分類： 消費(fèi)家電
英文描述： 210MHz Triple Video Digitizer with Digital PLL
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： 14 X 20 MM, ROHS COMPLIANT, MS-022, MQFP-128
文件頁數(shù)： 10/29頁
文件大?。?/td> 294K
代理商： X98021L128-3.3-Z
10
FN8219.0
June 2, 2005
HS
OUT
125
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals)
VS
OUT
126
3.3V digital output.Artificial VSYNC output aligned with pixel data. VSYNC is generated 8 pixel clocks after
the trailing edge of HS
OUT
.
This signal is usually not needed - use VSYNC
OUT
as VSYNC source.
HSYNC
OUT
127
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used to measure HSYNC
period. HS
OUT
should be used to detect the beginning of a line. This output will pass composite sync signals
and Macrovision signals if present on HSYNC
IN
or SOG
IN
.
VSYNC
OUT
128
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a
frame and measure the VSYNC period.
V
A
6, 11, 18, 20,
29, 35
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND
A
with 0.1μF.
GND
A
3, 5, 8, 10, 15,
17, 21, 23, 27,
30, 36
Ground return for V
A
and V
BYPASS
.
V
D
54, 67, 77, 89,
99, 111, 124
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND
D
with 0.1μF.
GND
D
32, 43, 51, 53,
66, 76, 78, 88,
98, 108, 110,
120, 123
Ground return for V
D
, V
CORE
, V
COREADC
, and V
PLL
.
V
X
38
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND
X
with 0.1μF.
GND
X
37
Ground return for V
X
.
V
BYPASS
4, 9, 16
Bypass these pins to GND
A
with 0.1μF. Do not connect these pins to each other or anything else.
VREG
IN
65
3.3V input voltage for V
CORE
voltage regulator. Connect to a 3.3V source, and bypass to GND
D
with 0.1μF.
VREG
OUT
64
Regulated output voltage for V
PLL
, V
COREADC
and V
CORE
; typically 1.9V. Connect only to V
PLL
,
V
COREADC
and V
CORE
and bypass at input pins as instructed below. Do not connect to anything else - this
output can only supply power to V
PLL
, V
COREADC
and V
CORE
.
V
COREADC
31
Internal power for the ADC’s digital logic. Connect to VREG
OUT
through a 10
Ω
resistor and bypass to GND
D
with 0.1μF.
V
PLL
42
Internal power for the PLL’s digital logic. Connect to VREG
OUT
through a 10
Ω
resistor and bypass to GND
D
with 0.1μF.
V
CORE
52, 79, 109
Internal power for core logic. Connect to VREG
OUT
and bypass each pin to GND
D
with 0.1μF.
NC
1, 2, 63
Reserved. Do not connect anything to these pins.
Pin Descriptions
(Continued)
SYMBOL
PIN
DESCRIPTION
X98021
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