參數(shù)資料
型號(hào): X96012
廠商: Intersil Corporation
英文描述: Universal Sensor Conditioner with Dual Look-up Table Memory and DACs(通用傳感器調(diào)節(jié)器,帶雙查找表存儲(chǔ)器及DACs)
中文描述: 通用傳感器護(hù)發(fā)雙查找表內(nèi)存和DAC(通用傳感器調(diào)節(jié)器,帶雙查找表存儲(chǔ)器及數(shù)模轉(zhuǎn)換器-)
文件頁數(shù): 5/23頁
文件大?。?/td> 353K
代理商: X96012
5
FN8216.3
February 20, 2008
A/D Converter Characteristics
I
OVER
I1 or I2 Overshoot on D/A Converter Data Byte
Transition
DAC input byte changing from 00h to
FFh and vice versa, V(I1) and V(I2)
are V
CC
- 1.2V in source mode and
1.2V in sink mode. (Note 2)
0
μA
I
UNDER
I1 or I2 Undershoot on D/A Converter Data Byte
Transition
0
μA
t
rDAC
I1 or I2 Rise Time on D/A Converter Data Byte
Transition; 10% to 90%
5
30
μs
TCO
I1I2
Temperature Coefficient of Output Current I1 or
I2 when Using Internal Resistor Setting
Bits I1FSO[1:0] | 00
2
or
Bits I2FSO[1:0] | 002,
VRMbit = “1”
See Figure 8
±200
ppm/°C
NOTES:
9. DAC input Byte = FFh, Source or sink mode.
10. LSB is defined as
11. Offset
DAC
: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in
LSB. FSError
DAC
: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is
expressed in LSB. The Offset
DAC
is subtracted from the measured value before calculating FSError
DAC
.DNL
DAC
: The Differential Non-Linearity of
a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one
code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNL
DAC
. INL
DAC
: The
Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the measured transfer
curve for Offset and Full Scale Error. It is expressed in LSB.
12. V(I1) and V(I2) are V
CC
- 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies < 1%.
13. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum V
CC
= 4.5V. The compliance
voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%.
divided by the resistance between R
1
or R
2
to V
SS
.
D/A Converter Characteristics
(See “Electrical Specifications” table starting on page 3 for standard conditions).
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
2
3
V(VRef)
255
x
[
]
(See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
ADCTIME
A/D Converter Conversion Time
Proportional to A/D converter input voltage.
This value is maximum at full scale input of
A/D converter. ADCfiltOff = “1”
9
ms
RIN
ADC
VSense Pin Input Resistance
VSense as an input, ADCIN bit = “1”
100
k
Ω
CIN
ADC
VSense Pin Input Capacitance
VSense as an input, ADCIN bit = “1”,
Frequency = 1 MHz. (Note 2)
1
7
pF
VIN
ADC
VSense Input Signal Range
This is the A/D Converter Dynamic
Range. ADCIN bit = “1”
0
V(VRef)
V
THE ADC IS MONOTONIC
Offset
ADC
A/D Converter Offset Error
(Notes 2, 14)
±1
LSB
FSError
ADC
A/D Converter Full Scale Error
±1
LSB
DNL
ADC
A/D Converter Differential
Nonlinearity
±0.5
LSB
INL
ADC
A/D Converter Integral Nonlinearity
±1
LSB
TempStep
ADC
Temperature Step Causing One
Step Increment of ADC Output
(Note 2)
0.52
0.55
0.58
°C
Out25
ADC
ADC Output at +25°C
01110101
2
X96012
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