參數(shù)資料
型號: X96010
廠商: Intersil Corporation
英文描述: Sensor Conditioner with Dual Look Up Table Memory and DACs(傳感器調(diào)節(jié)器,帶雙查找表存儲器及DACs)
中文描述: 傳感器護(hù)發(fā)高達(dá)表內(nèi)存和DAC(傳感器調(diào)節(jié)器,帶雙查找表存儲器及DAC的雙查找)
文件頁數(shù): 13/26頁
文件大小: 372K
代理商: X96010
13
FN8214.1
October 25, 2005
L2DAS: LUT2 D
IRECT
A
CCESS
S
ELECT
B
IT
(N
ON
-
VOLATILE
)
When bit L2DAS is set to “0” (default), LUT2 is
addressed by the output of the on-chip A/D converter.
When bit L2DAS is set to “1”, LUT2 is addressed by
bits L2DA5 - L2DA0.
D2DAS: D/A 2 D
IRECT
A
CCESS
S
ELECT
B
IT
(N
ON
-
VOLATILE
)
When bit D2DAS is set to “0” (default), the input to the
D/A converter 2 is a row of LUT2. When bit D2DAS is set
to “1”, that input is the content of the Control register 4.
Control Register 6
This register is accessed by performing a Read or
Write operation to address 86h of memory.
WEL: W
RITE
E
NABLE
L
ATCH
(V
OLATILE
)
The WEL bit controls the Write Enable status of the
entire X96010 device. This bit must be set to “1” before
any other Write operation (volatile or nonvolatile). Oth-
erwise, any proceeding Write operation to memory is
aborted and no ACK is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the “0”
state (disabled). The WEL bit is enabled by writing
10000000
2
to Control register 6. Once enabled, the
WEL bit remains set to “1” until the X96010 is powered
down, and then up again, or until it is reset to “0” by
writing 00000000
2
to Control register 6.
A Write operation that modifies the value of the WEL bit
will not cause a change in other bits of Control register 6.
Status Register - ADC Output
This register is accessed by performing a Read opera-
tion to address 87h of memory.
AD7 - AD0: A/D C
ONVERTER
O
UTPUT
B
ITS
(R
EAD
ONLY
)
These eight bits are the binary output of the on-chip
A/D converter. The output is 00000000
2
for minimum
input and 11111111
2
for full scale input. The six
MSBs select a row of the LUTs.
X96010
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