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參數(shù)資料
| 型號(hào)： | X95840 |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | Quad Digital Controlled Potentiometers (XDCP)(四數(shù)控電位器（XDCP）) |
| 中文描述： | 四數(shù)字（數(shù)字電位器）（四數(shù)控電位器（數(shù)字電位器）控制電位器） |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | X95840 |
11 of 12
REV 1.16 7/28/04
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X95840
WRITE OPERATION
A Write operation requires a START condition, followed
by a valid Identification Byte, a valid Address Byte, a Data
Byte, and a STOP condition. After each of the three
bytes, the X95840 responds with an ACK. At this time, if
the Data Byte is to be written only to volatile registers,
then the device enters its standby state. If the Data Byte
is to be written also to non-volatile memory, the X95840
begins its internal write cycle to non-volatile memory.
During the internal non-volatile write cycle, the device
ignores transitions at the SDA and SCL pins, and the
SDA output is at a high impedance state. When the
internal non-volatile write cycle is completed, the X95840
enters its standby state. See Figure 3.
The byte at address 00001000 bin (8 decimal)
determines if the Data Byte is to be written to volatile and/
or non-volatile memory. See “Memory Description” on
page 3.
DATA PROTECTION
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP is active (LOW) the
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead,
goes to its standby state waiting for a new START
condition.
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and
total number of SCL pulses act as a protection of both
volatile and non-volatile registers. During a Write
sequence, the Data Byte is loaded into an internal shift
register as it is received. If the Address Byte is 0, 1, 2, 3,
or 8 decimal, the Data Byte is transferred to the
appropriate Wiper Register (WR) or to the Access Control
Register, at the falling edge of the SCL pulse that loads
the last bit (LSB) of the Data Byte. If the Address Byte is
between 0 and 6 (inclusive), and the Access Control
Register is all zeros (default), then the STOP condition
initiates the internal write cycle to non-volatile memory.
READ OPERATION:
A Read operation consist of a three byte instruction
followed by one or more Data Bytes (See Figure 4). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
bit set to “0”, an Address Byte, a second START, and a
second Identification byte with the R/W bit set to “1”.
After each of the three bytes, the X95840 responds with
an ACK. Then the X95840 transmits Data Bytes as long
as the master responds with an ACK during the SCL
cycle following the eigth bit of each byte. The master
terminates the read operation (issuing a STOP
condition) following the last bit of the last Data Byte. See
Figure 4.
The Data Bytes are from the memory location indicated
by an internal pointer. This pointer initial value is
determined by the Address Byte in the Read operation
instruction, and increments by one during transmission of
each Data Byte. After reaching the memory location 01Fh
(8 decimal) the pointer “rolls over” to 00h, and the device
continues to output data for each ACK received.
The byte at address 00001000 bin (8 decimal)
determines if the Data Bytes being read are from volatile
or non-volatile memory. See “Memory Description” on
page 3.
Signals
from the
Master
Signals from
the Slave
Signal at
SDA
S
t
a
r
t
Identification
Byte
with
R/W=0
Address
Byte
A
C
K
A
C
K
1
0
1
0
0
S
t
o
p
A
C
K
1
1
1
0
0
Identification
Byte
with
R/W=1
A
C
K
S
t
a
r
t
Last Read
Data Byte
First Read
Data Byte
A
C
K
Figure 4. Read Sequence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X95840_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digital Controlled Potentiometers |
| X95840UV20I-2.7 | 功能描述:IC XDCP QUAD 256TAP 50K 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 50 ppm/°C 存儲(chǔ)器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細(xì)型，TSOT-23-6 供應(yīng)商設(shè)備封裝:TSOT-23-6 包裝:帶卷 (TR) |
| X95840UV20I-2.7T1 | 功能描述:IC XDCP QUAD 256TAP 50K 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 50 ppm/°C 存儲(chǔ)器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細(xì)型，TSOT-23-6 供應(yīng)商設(shè)備封裝:TSOT-23-6 包裝:帶卷 (TR) |
| X95840UV20IZ-2.7 | 功能描述:IC XDCP QUAD 256TAP 50K 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):2 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲(chǔ)器類型:易失 接口:6 線串行（芯片選擇，遞增，增/減） 電源電壓:2.6 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| X95840UV20IZ-2.7T1 | 功能描述:IC POT DGTL QUAD 50K OHM 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):2 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲(chǔ)器類型:易失 接口:6 線串行（芯片選擇，遞增，增/減） 電源電壓:2.6 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
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