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參數(shù)資料
| 型號： | X9470V24I |
| 英文描述： | RF Power Amplifier (PA) Bias Controller |
| 中文描述： | 射頻功率放大器（PA）的偏置控制器 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 542K |
| 代理商： | X9470V24I |
comparator. V
REF
can be a fixed reference voltage or
adjusted by using the 64-tap digital potentiometer. The
output of the comparator is used to increment or decre-
ment the R
BIAS
potentiometer in the Bias Adjustment
Circuit Block. The gain factor K
1
is designed such that
Preliminary Information
X9470
12 of 25
REV 11.16 3/20/03
www.xicor.com
Figure 1. Typical Application
X9470 FUNCTIONAL DESCRIPTION
This section provides detail description of the following:
– Sense and Scale Block Description
– Bias Adjustment Control Block Description
– Output Block Description
– Bias Adjustment and Storage Description
SENSE AND SCALE BLOCK
The Sense and Scale Circuit Block (Figure 2) implements
an instrumentation amplifier whose inputs (V
SENSE+
and
V
SENSE-
) are across an external sense resistor in the
drain circuit of an RF Power FET. V
SENSE+
is connected
to V
DD
, the drain voltage source for the RF power FET,
and V
SENSE-
pin is connected to the other end the exter-
nal sense resistor.
An internal instrumentation amplifier (IA) will sense the
V and amplify it by a gain factor of K
1
(see Equation
1). The resulting output is compared with V
REF
at the
the Sense and Scale Block will set the Bias Adjustment
Circuit Block to operate in a given voltage range (mV)
vs. drain current adjustment (mA).
V
REF
K
1
* R
SENSE
K
1
is fixed 50x for the internal comparator input.
The output of the IA is also available at the pin Vout to
enable drain current monitoring. The gain at Vout is
fixed at a factor of K
2
, lower than K
1
so that high I
DQ
currents will not cause saturation of the Vout signal.
The equation for Vout is given as:
V = I
DQ
* R
SENSE
V
OUT
= K
2
*
V
K
2
is fixed to 20x for the Vout pin
BIAS ADJUSTMENT CIRCUIT BLOCK
There are three sections of this block (Figure 3): the
input control, counter and decode section (1), the
resistor array (2); and the non-volatile register (3). The
input control section operates just like an up/down
counter. The input of the counter is driven from the out-
put of the comparator in the Sense and Scale Block
and is clocked by the SCL signal. The output of this
counter is decoded to select one of the taps of a 256-
tap digital potentiometer.
A0
A2
VCC
VSS
V+
AGND
Comparator
choke
RF PA in
R
SENSE
V
DD
V
REF
V
SENSE+
V
BIAS
INC/DEC
Instrumentation
Amplifier
V
CS
V
OUT
V
SENSE–
R
REF
RW
REF
RL
REF
SHDN
+
–
EEPROM
SCL
SDA
A1
Vbias
control
VREF
control
I2C
interface
Control &
Status Registers
RF
out
RH
REF
R
BIAS
VP
RH
BIAS
RL
BIAS
RW
BIAS
FILTER
V
B
RF Impedance
Matching
C
BULK
Class A Example
I
DQ
(1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X9470 | RF Power Amplifier (PA) Bias Controller |
| X9470V24I | RF Power Amplifier (PA) Bias Controller |
| X9511(中文) | PushPot Potentiometer (Push Button Controlled)(32個抽頭,按鈕控制,非易失性數(shù)字電位器) |
| X9511 | PushPot Potentiometer (Push Button Controlled)(32個抽頭,按鈕控制,非易失性數(shù)字電位器) |
| X9514(中文) | PushPot Potentiometer (Push Button Controlled)(32個抽頭,對數(shù)電阻特性,按鈕控制,非易失性數(shù)字電位器) |
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