參數(shù)資料
型號(hào)： X9448YV24I
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計(jì)
英文描述： Mixed Signal with 2-Wire Interface
中文描述： 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24
封裝： PLASTIC, TSSOP-24
文件頁(yè)數(shù)： 5/20頁(yè)
文件大小： 127K
代理商： X9448YV24I
X9448
Characteristics subject to change without notice.
5 of 20
REV 1.0 6/21/00
www.xicor.com
Figure 3. Two-Byte Command Sequence
Figure 4. Three-Byte Command Sequence
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
P1
P0
A
C
K
SCL
SDA
S
T
O
P
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
P1 P0 R1 R0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
D5 D4 D3 D2
D1 D0
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers
that is to be acted upon when a register oriented
instruction is issued. The last two bits (P1 and P0)
select which one of the two potentiometers or which
one of the two voltage comparators is to be affected by
the instruction.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the wiper counter register or
analog control register and one of the data registers. A
transfer from a data register to a wiper counter register
or analog control register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed t
STPWV
. A transfer from the Wiper
Counter Register current wiper position to a data regis-
ter is a write to nonvolatile memory and takes a mini-
mum of t
WR
to complete. The transfer can occur
between one of the two potentiometers or one of the
two voltage comparators and one of its associated reg-
isters; or it may occur globally, wherein the transfer
occurs between both of the potentiometers and voltage
comparators and one of their associated registers.
Four instructions require a three-byte sequence to
complete. The basic sequence is illustrated in Figure 4.
These instructions transfer data between the host and
the X9448; either between the host and one of the data
registers or directly between the host and the wiper
counter and analog control registers. These instruc-
tions are: read wiper counter register or analog control
register, read the current wiper position of the selected
pot or the comparator control bits, Write wiper counter
register or analog control register, i.e. change current
wiper position of the selected pot or control the voltage
comparator; read data register, read the contents of the
selected nonvolatile register; write data register, write a
new value to the selected data register. The bit struc-
tures of the instructions are shown in Figure 6.
The increment/decrement command is different from
the other commands. Once the command is issued
and the X9448 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t
HIGH
) while SDA is HIGH, the selected wiper will
move one resistor segment towards the V
H
terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V
L
terminal. A detailed illustration of the
sequence for this operation is shown in Figure 5.
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