參數(shù)資料
型號(hào)： X9428YV14IZ-2.7
廠商： Intersil
文件頁數(shù)： 6/21頁
文件大小： 0K
描述： IC DGTL POT 2K 1CH 14TSSOP
標(biāo)準(zhǔn)包裝： 95
系列： XDCP™
接片： 64
電阻（歐姆）： 2k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類型： 非易失
接口： 串行
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 管件
14
FN8197.1
April 26, 2006
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP AND POWER-DOWN
There are no restrictions on the power-up or power-down sequencing of the bias supplies VCC, V+, and V- provided
that all three supplies reach their final values within 1msec of each other. However, at all times, the voltages on the
potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory
is not in effect until all supplies reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
Symbol
Parameter
Limits
Test Conditions
Min.
Typ.
Max.
Unit
ICC1
VCC supply current
(nonvolatile write)
1mA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ICC2
VCC supply current
(move wiper, write, read)
100
A
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ISB
VCC current (standby)
1
A
SCL = SDA = VCC, Addr. = VSS
ILI
Input leakage current
10
A
VIN = VSS to VCC
ILO
Output leakage current
10
A
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC x 0.5
V
VIL
Input LOW voltage
-0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
Years
Symbol
Test
Max.
Unit
Test Conditions
CI/O(5)
Input/output capacitance (SDA)
8
pF
VI/O = 0V
CIN(5)
Input capacitance (A0, A1, A2, A3, and SCL)
6
pF
VIN = 0V
Symbol
Parameter
Min.
Typ.
Max.
Unit
tPUR(6)
Power-up to initiation of read operation
1
ms
tPUW(6)
Power-up to initiation of write operation
5
ms
tRVCC(7)
VCC Power-up ramp rate
0.2
50
V/msec
X9428
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