參數(shù)資料
型號: X9428WSI-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Single Digitally Controlled Potentiometer
中文描述: 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO16
封裝: 0.300 INCH, PLASTIC, SOIC-16
文件頁數(shù): 5/20頁
文件大?。?/td> 580K
代理商: X9428WSI-2.7
X9428
Characteristics subject to change without notice.
5 of 20
REV 1.1.5 7/8/03
www.xicor.com
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t
HIGH
) while SDA is HIGH, the selected wiper will
move one resistor segment towards the V
terminal. Similarly, for each SCL clock pulse while SDA
is LOW, the selected wiper will move one resistor
segment towards the V
L
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
H
/R
H
/R
L
terminal. A detailed
Table 1. Instruction Set
Note:
(7) 1/0 = data is one or zero
Instruction
Instruction Set
I
0
R
0
1
Operation
I
1
3
I
0
2
I
1
1
R
0
0
X
1
0
X
0
0
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
0
Read the contents of the Wiper Counter Register
1
0
1
0
0
0
0
0
Write new value to the Wiper Counter Register
1
0
1
1
1/0
1/0
0
0
Read the contents of the Data Register pointed to
by R
1
–R
0
Write new value to the Data Register pointed to by
R
1
–R
0
Transfer the contents of the Data Register pointed
to by R
1
–R
0
to its Wiper Counter Register
Transfer the contents of the Wiper Counter Register
to the Data Register pointed to by R
1
–R
0
Enable Increment/decrement of the Wiper Counter
Register
Write Data Register
1
1
0
0
1/0
1/0
0
0
XFR Data Register to
Wiper Counter Register
XFR Wiper Counter
Register to Data Register
Increment/Decrement
Wiper Counter Register
1
1
0
1
1/0
1/0
0
0
1
1
1
0
1/0
1/0
0
0
0
0
1
0
0
0
0
1/0
Figure 3. Two-Byte Instruction Sequence
S
T
A
R
T
0
1
0
1
A3
A2
0
A0
A
C
K
I3
I2
I1
I0
R1
R0
0
0
A
C
K
SCL
SDA
S
T
O
P
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