參數(shù)資料
型號: X9428WPI-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Single Digitally Controlled Potentiometer
中文描述: 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 9/20頁
文件大小: 580K
代理商: X9428WPI-2.7
X9428
Characteristics subject to change without notice.
9 of 20
REV 1.1.5 7/8/03
www.xicor.com
Instruction Format
Notes:
(1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
S
A
C
K
wiper position
(sent by slave on SDA)
M
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
0
A
0
1
0
0
1
0
0
0
0
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
S
A
C
K
wiper position
(sent by master on SDA)
S
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
0
A
0
1
0
1
0
0
0
0
0
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
register
addresses
S
A
C
K
wiper position/data
(sent by slave on SDA)
M
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
0
A
0
1
0
1
1
R
1
R
0
0
0
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
register
addresses
S
A
C
K
wiper position/data
(sent by master on SDA)
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1
A
3
A
2
0
A
0
1 1 0 0
R
1
R
0
0 0
0 0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
register
addresses
S
A
C
K
S
T
O
P
0 1 0 1
A
3
A
2
0
A
0
1 1 0 1
R
1
R
0
0 0
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