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參數(shù)資料
| 型號： | X9421YV14ZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP SGL 64-TAP 2.5K 14-TSSOP |
| 標準包裝： | 2,500 |
| 系列： | XDCP™ |
| 接片： | 64 |
| 電阻（歐姆）： | 2.5k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 5 線 SPI（芯片選擇，設備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
12
FN8196.4
January 14, 2009
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Power-up Requirements
(Power-up sequencing can affect correct recall of the wiper
registers) The preferred power-on sequence is as follows:
First VCC and then the potentiometer pins, RH, RL, and RW.
Voltage should not be applied to the potentiometer pins
before VCC is applied. The VCC ramp rate specification
should be met, and any glitches or slope changes in the VCC
line should be held to <100mV if possible. Also, VCC should
not reverse polarity by more than 0.5V. Recall of wiper
position will not be complete until VCC reaches its final
value.
DC Electrical Specifications
(Over the recommended operating conditions unless otherwise specified).
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN
(Note 5)
TYP
(Note 6)
MAX
(Note 5)
UNITS
ICC1
VCC Supply Current
(Active)
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
400
A
ICC2
VCC Supply Current
(Nonvolatile Write)
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
3.5
mA
ISB
VCC Current (Standby)
SCK = SI = VSS, Addr. = VSS
3A
ILI
Input Leakage Current
VIN = VSS to VCC
10
A
ILO
Output Leakage Current
VOUT = VSS to VCC
10
A
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 0.3
V
VIL
Input LOW Voltage
-0.5
VCC x 0.1
V
VOL
Output LOW Voltage
IOL = 3mA
0.4
V
PARAMETER
MIN
UNITS
Minimum Endurance
100,000
Data Changes per Bit per Register
Data Retention
100
Years
SYMBOL
TEST
TYP
UNITS
TEST CONDITIONS
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (A0, SI, and SCK)
6
pF
VIN = 0V
SYMBOL
PARAMETER
MIN
MAX
UNITS
VCC Power-up Ramp
0.2
50
V/msec
NOTES:
1. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = RTOT/63 or (VH - VL)/63, single pot
4. Typical = Individual array resolution.
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
6. Limits should be considered typical and are not production tested.
7.
This parameter is not production tested. Parameter established by characterization.
X9421
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