參數(shù)資料
型號: X9421WSI-2.7
元件分類: 數(shù)字電位計
英文描述: Single Digitally Controlled (XDCP) Potentiometer
中文描述: 單數(shù)控(數(shù)字電位器)電位
文件頁數(shù): 13/21頁
文件大小: 117K
代理商: X9421WSI-2.7
X9421
REV 1.1.6 8/1/02
Characteristics subject to change without notice.
13 of 21
www.xicor.com
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER UP REQUIREMENTS
(Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V
CC
and then the potentiometer pins, R
H
, R
L
, and R
W
.
Voltage should not be applied to the potentiometer pins before V
CC
is applied. The V
CC
ramp rate specification
should be met, and any glitches or slope changes in the V
CC
line should be held to <100mV if possible. Also, V
CC
should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until V
CC
reaches its
final value.
Notes:
(5) This parameter is periodically sampled and not 100% tested.
A.C. TEST CONDITIONS
Symbol
I
CC1
Parameter
Limits
Test Conditions
f
SCK
= 2MHz, SO = Open,
Other Inputs = V
SS
f
SCK
= 2MHz, SO = Open,
Other Inputs = V
SS
SCK = SI = V
SS
, Addr. = V
SS
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
Min.
Typ.
Max.
400
Units
μA
V
CC
Supply Current
(Active)
V
CC
Supply Current
(Non-volatile Write)
V
CC
Current (Standby)
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
I
CC2
1
mA
I
SB
I
LI
I
LO
V
IH
V
IL
V
OL
1
10
10
μ
A
μ
A
μ
A
V
V
V
V
CC
x 0.7
–0.5
V
CC
+ 0.5
V
CC
x 0.1
0.4
I
OL
= 3mA
Parameter
Minimum Endurance
Data Retention
Min.
100,000
100
Units
Data Changes per Bit per Register
Years
Symbol
C
OUT
(5)
C
IN
(5)
Test
Max.
8
6
Units
pF
pF
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Output Capacitance (SO)
Input Capacitance (A0, SI, and SCK)
Symbol
t
R
V
CC
(5)
Parameter
V
CC
Power up Ramp
Max.
0.2
Max.
50
Units
V/msec
I
nput pulse levels
V
CC
x 0.1 to V
CC
x
0.9
10ns
V
CC
x 0.5
Input rise and fall times
Input and output timing level
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