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參數(shù)資料
| 型號： | X9421WS16I |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Single Digitally Controlled (XDCP) Potentiometer |
| 中文描述： | 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO16 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 117K |
| 代理商： | X9421WS16I |
X9421
REV 1.1.6 8/1/02
Characteristics subject to change without notice.
6 of 21
www.xicor.com
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
INSTRUCTIONS
Address/Identification (ID) Byte
The first byte sent to the X9421 from the host, following
a CS going HIGH to LOW, is called the Address or
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9421 this is fixed as 0101[B] (refer to Figure 2).
The least significant bit in the ID byte selects one of
two devices on the bus. The physical device address is
defined by the state of the A
0
input pin. The X9421
compares the serial data stream with the address input
state; a successful compare of the address bit is
required for the X9421 to successfully continue the
command sequence. The A
0
input can be actively
driven by a CMOS input signal or tied to V
CC
or V
SS
.
The remaining three bits in the ID byte must be set to
110.
Figure 2. Address/Identification Byte Format
Instruction Byte
The next byte sent to the X9421 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next two
bits point to one of four Data Registers. The format is
shown below in Figure 3.
Figure 3. Instruction Byte Format
1
0
0
1
1
0
A0
Device Type
Identifier
Device Address
1
I1
I2
I3
I0
R1
R0
0
0
Register
Select
Instructions
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry
Register 0
Register 1
REGISTER 2
REGISTER 3
Serial
Bus
Input
Parallel
Bus
Input
Counter
Register
(WCR)
INC/DEC
Logic
UP/DN
CLK
Modified SCK
UP/DN
V
H
V
L
V
W
8
6
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN V
W
= V
L
IF WCR = 3F[H] THEN V
W
= V
H
Wiper
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