參數(shù)資料
型號： X9418YS24Z-2.7
廠商： Intersil
文件頁數(shù)： 14/20頁
文件大小： 0K
描述： IC XDCP DUAL 64TAP 2.5K 24-SOIC
標準包裝： 30
系列： XDCP™
接片： 64
電阻（歐姆）： 2.5k
電路數(shù)： 2
溫度系數(shù)： 標準值 ±300 ppm/°C
存儲器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC
包裝： 管件
3
FN8194.3
October 12, 2006
PIN CONFIGURATION
PIN NAMES
PRINCIPLES OF OPERATION
The X9418 is a highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9418 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9418 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9418 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9418 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
Symbol
Description
SCL
Serial Clock
SDA
Serial Data
A0 - A3
Device Address
VH0/RH0 - VH1/RH1,
VL0/RL0 - VL1/RL1
Potentiometer Pins
(terminal equivalent)
VW0/RW0 -
VW1/RW1
Potentiometer Pins
(wiper equivalent)
WP
Hardware Write Protection
V+,V-
Analog Supplies
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
VCC
RL0/VL0
RH0/VH0
WP
SDA
A1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
5
V+
NC
A0
NC
A3
SCL
NC
DIP/SOIC
X9418
VSS
RW0/VW0
14
13
11
12
A2
RL1/VL1
RH1/VH1
RW1/VW1
NC
V-
SDA
A1
RL1/VL1
VSS
NC
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
WP
A2
VW0/RW0
VH0/RH0
VL0/RL0
VCC
NC
V+
X9418
A3
RH1/VH1
14
13
11
12
RW1/VW1
NC
V-
SCL
A0
NC
TSSOP
X9418
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