Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X94" />
參數(shù)資料
型號: X9418WV24IZT1
廠商: Intersil
文件頁數(shù): 12/20頁
文件大小: 0K
描述: IC XDCP DUAL 64TAP 10K 24-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: XDCP™
接片: 64
電阻(歐姆): 10k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
2
FN8194.3
October 12, 2006
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9418.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Device Address (A0 - A3)
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with
the
Address
input
in
order
to
initiate
communication with the X9418. A maximum of 16
devices may occupy the 2-wire serial bus.
Potentiometer Pins
VH/RH (VH0/RH0 - VH1/RH1), VL/RL (VL0/RL0 - VL1/RL1)
The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
VW/RW (VW0/RW0 - VW1/RW1)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages
for the XDCP analog section.
Ordering Information
PART NUMBER
PART MARKING
VCC LIMITS
(V)
POTENTIOMET
ER
ORGANIZATION
(k
Ω)
TEMPERATU
RE RANGE
(°C)
PACKAGE
PKG. DWG. #
X9418WV24*
X9418WV
5 ±10%
10
0 to +70
24 Ld TSSOP (4.4MM)
MDP0044
X9418WV24Z* (Note)
X9418WV Z
0 to +70
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
X9418WP24I-2.7
X9418WP G
2.7 to 5.5
10
-40 to +85
24 Ld PDIP
E24.6
X9418WS24I-2.7
X9418WS G
-40 to +85
24 Ld SOIC (300MIL)
M24.3
X9418WS24IZ-2.7 (Note)
X9418WS ZG
-40 to +85
24 Ld SOIC (300MIL) (Pb-free)
M24.3
X9418WV24-2.7*
X9418WV F
0 to +70
24 Ld TSSOP (4.4MM)
MDP0044
X9418WV24Z-2.7* (Note) X9418WV ZF
0 to +70
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
X9418WV24I-2.7
X9418WV G
-40 to +85
24 Ld TSSOP (4.4MM)
MDP0044
X9418WV24IZ-2.7 (Note)
X9418WV ZG
-40 to +85
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
X9418YS24-2.7
X9418YS F
2.5
0 to +70
24 Ld SOIC (300MIL)
M24.3
X9418YS24Z-2.7 (Note)
X9418YS ZF
0 to +70
24 Ld SOIC (300MIL) (Pb-free)
M24.3
X9418YS24I-2.7
X9418YS G
-40 to +85
24 Ld SOIC (300MIL)
M24.3
X9418YS24IZ-2.7 (Note)
X9418YS ZG
-40 to +85
24 Ld SOIC (300MIL) (Pb-free)
M24.3
X9418YV24I-2.7*
X9418YV G
-40 to +85
24 Ld TSSOP (4.4MM)
MDP0044
X9418YV24IZ-2.7* (Note) X9418YV ZG
-40 to +85
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9418
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