參數(shù)資料
型號: X9418WP24I
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: SHIELDED NULL MODEM CBL DB25 MALE - DB25 FEMALE
中文描述: DUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDIP24
封裝: PLASTIC, DIP-24
文件頁數(shù): 2/21頁
文件大小: 386K
代理商: X9418WP24I
X9418
Characteristics subject to change without notice.
2 of 21
REV 1.1.5 7/23/02
www.xicor.com
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9418.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Device Address (A
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9418. A maximum of 16
devices may occupy the 2-wire serial bus.
0
A
3
)
Potentiometer Pins
V
The V
terminal connections on either end of a mechanical
potentiometer.
H
/R
H
(V
H0
/R
/R
and V
H0
—V
H1
/R
/R
H1
inputs are equivalent to the
), V
L
/R
L
(V
L0
/R
L0
—V
L1
/R
L1
)
H
H
L
L
V
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
W
/R
W
(V
W0
/R
W0
—V
W1
/R
W1
)
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages
for the XDCP analog section.
PIN CONFIGURATION
PIN NAMES
Symbol
Description
SCL
SDA
A0-A3
V
H0
V
L0
V
W0
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometer Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection
/R
/R
H0
L0
–V
–V
H1
L1
–V
/R
/R
H1
L1
/R
,
/R
W0
W1
W1
WP
V+,V-
V
CC
V
SS
NC
V
CC
R
L0
/V
L0
R
H0
/V
H0
R
W0
/V
W0
WP
SDA
A1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
5
14
13
V+
NC
NC
NC
A0
NC
A3
SCL
NC
NC
NC
DIP/SOIC
X9418
V
SS
A2
R
L1
/V
L1
R
H1
/V
H1
R
W1
/V
W1
V-
SDA
A1
R
L1
/V
L1
R
H1
/V
H1
R
W1
/V
W1
V
SS
NC
NC
NC
V-
SCL
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
WP
A2
V
W0
/R
W0
V
H0
/R
H0
V
L0
/R
L0
V
CC
NC
NC
NC
V+
A0
NC
X9418
A3
TSSOP
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