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參數(shù)資料
| 型號： | X9417WS24I |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | DUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24 |
| 封裝： | PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 385K |
| 代理商： | X9417WS24I |
X9417
Characteristics subject to change without notice.
12 of 21
REV 1.1.4 7/22/02
www.xicor.com
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH—RL)/63, single pot
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then V+ and V–, and then the potentiometer pins, RH,
RL, and RW. Voltage should not be applied to the potentiometer pins before V+ or V– is applied. The VCC ramp rate
specication should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possi-
ble. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until VCC,
V+ and V– reach their nal value.
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specic
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(6) This is not guaranteed or tested parameter and should only be used as a guidance.
Symbol
Parameter
Limits
Test Conditions
Min.
Typ.
Max.
Unit
ICC1
VCC supply current
(nonvolatile write)
1mA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ICC2
VCC supply current
(move wiper, write, read)
100
A
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ISB
VCC current (standby)
1
A
SCL = SDA = VCC, Addr. = VSS
ILI
Input leakage current
10
A
VIN = VSS to VCC
ILO
Output leakage current
10
A
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW voltage
–0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
Years
Symbol
Test
Max.
Unit
Test Conditions
CI/O
(4)
Input/output capacitance (SDA)
8
pF
VI/O = 0V
CIN
(4)
Input capacitance (A0, A1, A2, A3, and SCL)
6
pF
VIN = 0V
Symbol
Parameter
Min.
Typ.
Max.
Unit
tPUR
(5)
Power-up to initiation of read operation
1
ms
tPUW
(5)
Power-up to initiation of write operation
5
ms
tRVCC
(6)
VCC Power up ramp rate
0.2
50
V/msec
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