參數(shù)資料
型號: X9410YV24
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Low Noise/Low Power/SPI Bus
中文描述: DUAL 2.5K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24
封裝: 4.40 MM, TSSOP-24
文件頁數(shù): 12/21頁
文件大?。?/td> 123K
代理商: X9410YV24
X9410
Characteristics subject to change without notice.
12 of 21
REV 1.1 10/6/00
www.xicor.com
A.C. TEST CONDITIONS
Notes:
(5) This parameter is periodically sampled and not 100%
tested
(6) t
PUR
and t
PUW
are the delays required from the time the
third (last) power supply (V
CC
, V+ or V-) is stable until the
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
Test Circuit #3 SPICE Macro Model
I
nput pulse levels
Input rise and fall times
Input and output timing level
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
10pF
R
H
R
TOTAL
C
H
25pF
C
W
C
L
10pF
R
W
R
L
AC TIMING
Symbol
f
SCK
t
CYC
t
WH
t
WL
t
LEAD
t
LAG
t
SU
t
H
t
RI
t
FI
t
DIS
t
V
t
HO
t
RO
t
FO
t
HOLD
t
HSU
t
HH
t
HZ
t
LZ
T
I
t
CS
t
WPASU
t
WPAH
Parameter
Min.
Max.
2.0
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
Lag time
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
SO output valid time
SO output hold time
SO output rise time
SO output fall time
HOLD time
HOLD setup time
HOLD hold time
HOLD low to output in high Z
HOLD high to output in low Z
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
WP, A0 and A1 setup time
WP, A0 and A1 hold time
500
200
200
250
250
50
50
2
2
0
500
100
0
50
50
400
100
100
100
100
20
2
0
0
相關(guān)PDF資料
PDF描述
X9410YV24-2.7 Low Noise/Low Power/SPI Bus
X9410YV24I Low Noise/Low Power/SPI Bus
X9410YV24I-2.7 Low Noise/Low Power/SPI Bus
X9410YV24IZ Low Noise/Low Power/SPI Bus
X9410YV24IZ-2.7 Low Noise/Low Power/SPI Bus
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