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參數(shù)資料
| 型號(hào)： | X9409WS24Z-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | Low Noise/Low Power/2-Wire Bus |
| 中文描述： | QUAD 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 407K |
| 代理商： | X9409WS24Z-2.7 |
X9409 – Preliminary Information
Characteristics subject to change without notice.
12 of 21
REV 1.6 1/30/03
www.xicor.com
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
CAPACITANCE
Symbol
C
I/O
(4)
C
IN
(4)
POWER-UP TIMING
Symbol
t
r
V
CC
(6)
POWER UP REQUIREMENTS
(Power Up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V
CC
, then the potentiometer pins, R
H
, R
L
, and R
W
. The V
CC
ramp rate specification should be met, and any glitches or slope changes in the V
CC
line should be held to <100mV
if possible. If V
CC
powers down, it should be held below 0.1V for more than 1 second before powering up again in
order for proper wiper register recall. Also, V
CC
should not reverse polarity by more than 0.5V. Recall of wiper
position will not be complete until V
CC
reaches its final value.
Notes:
(4) This parameter is periodically sampled and not 100% tested
(5) t
PUR
and t
PUW
are the delays required from the time the (last) power supply (V
CC
) is stable until the specific instruction can be
issued. These parameters are periodically sampled and not 100% tested.
(6) Sample tested only.
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Symbol
I
CC1
Parameter
Limits
Typ.
Test Conditions
f
SCL
= 400kHz, SDA = Open,
Other Inputs = V
SS
f
SCL
= 400kHz, SDA = Open,
Other Inputs = V
SS
SCL = SDA = V
CC
, Addr. = V
SS
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
Min.
Max.
100
Unit
μA
V
CC
supply current (Active)
I
CC2
V
CC
supply current
(Nonvolatile Write)
V
CC
current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
1
mA
I
SB
I
LI
I
LO
V
IH
V
IL
V
OL
1
10
10
μA
μA
μA
V
V
V
V
CC
x 0.7
–0.5
V
CC
+ 0.5
V
CC
x 0.1
0.4
I
OL
= 3mA
Min.
100,000
100
Unit
Data changes per bit per register
Years
Test
Max.
8
6
Unit
pF
pF
Test Conditions
V
I/O
= 0V
V
IN
= 0V
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3, and SCL)
Parameter
Min.
0.2
Max.
50
Unit
V/ms
V
CC
power-up rate
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