參數(shù)資料
型號(hào)： X9401WS24-2.7
元件分類(lèi)： 數(shù)字電位計(jì)
英文描述： QUAD 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24
封裝： PLASTIC, SOIC-24
文件頁(yè)數(shù)： 12/21頁(yè)
文件大?。?/td> 176K
代理商： X9401WS24-2.7
X9401 – Preliminary Information
Characteristics subject to change without notice.
2 of 21
REV 1.9 4/13/04
www.xicor.com
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9401.
Chip Select (CS)
When CS is HIGH, the X9401 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9401, placing it in
the active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial com-
munication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause fea-
ture is not used, HOLD should be held HIGH at all times.
Device Address (A0–A1)
The address inputs are used to set the least signicant 2 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address input
in order to initiate communication with the X9401. A
maximum of 4 devices may occupy the SPI serial bus.
Potentiometer Pins
VH (VH0–VH3), VL (VL0–VL3), RH (RH0–RH3),
RL (RL0–RL3)
The VH/RH and VL/RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
VW (VW0–VW3), RW (RW0–RW3)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Wiper Counter Registers.
PIN CONFIGURATION
VCC
VL0/RL0
VH0/RH0
WP
SI
A1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
NC
VL3/RL3
VH3/RH3
VW3/RW3
A0
SO
HOLD
SCK
VL2/RL2
VH2/RH2
SOIC
X9401
V
SS
VW0/RW0
14
13
11
12
CS
VL1/RL1
VH1/RH1
VW1/RW1
VW2/RW2
NC
SI
A1
VH2/RH2
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
WP
CS
VW0/RW0
VCC
NC
VL3/RL3
VH3/RH3
VW3/RW3
TSSOP
X9401
VW2/RW2
14
13
11
12
HOLD
VL1/RL1
VH1/RH1
VW1/RW1
A0
SO
VH0/RH0
NC
SCK
VL2/RL2
VL0/RL0
VSS
2
3
4
A
B
C
D
E
F
Top View–Bumps Down
VW0/RW0
VL0/RL0
NC
A0
HOLD
VL1/RL1
VCC
VL3/RL3
VW3/RW3
SO
SI
VW1/RW1
SCK
VL2/RL2
WP
NC
VH0/RH0 VH1/RH1
VH3/RH3 VH2/RH2
VSS
VW2/RW2
CS
A1
1
CSP
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