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參數(shù)資料
| 型號： | X9279UV14Z-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | EDN12 DB9 EMI/RFI FF 250F |
| 中文描述： | 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 398K |
| 代理商： | X9279UV14Z-2.7 |
X9279
Characteristics subject to change without notice.
5 of 24
REV 1.1.7 2/6/03
www.xicor.com
PRINCIPLES OF OPERATION
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
– Resistor Array Description.
– Serial Interface Description.
– Instruction and Register Description.
Array Description
The X9279 is comprised of a resistor array (see Figure
1). The array contains, in effect, 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
Power Up and Down Recommendations.
There are no restrictions on the power-up or power-
down conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
positive than or equal to V
H
, V
V
L
, V
W
. The V
CC
ramp rate specification is always in
effect.
CC
is always more
, i.e., V
CC
L
, and V
W
≥
V
H
,
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
REGISTER 1
(DR1)
REGISTER 2
(DR2)
REGISTER 3
(DR3)
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
R
H
R
L
R
W
8
8
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN R
W
= R
L
IF
WCR = FF[H]
THEN
R
W
=
R
H
WIPER
BANK_0 Only
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