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參數(shù)資料
| 型號： | X9271TV14ZT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 21/22頁 |
| 文件大小： | 0K |
| 描述： | IC XDCP SGL 256TAP 100K 14-TSSOP |
| 標準包裝： | 2,500 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 6 線 SPI（芯片選擇，設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
8
FN8174.3
June 23, 2011
DEVICE DESCRIPTION
Instructions
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bit is the device ID for the X9271; this is fixed as
0101[B] (Table 4).
The A1 - A0 bits in the ID byte are the internal slave
address. The physical device address is defined by
the state of the A1 - A0 input pins. The slave address
is externally specified by the user. The X9271
compares the serial data stream with the address
input state; a successful compare of both address bits
is required for the X9271 to successfully continue the
command sequence. Only the device for which slave
address matches the incoming device address sent by
the master executes the instruction. The A1 - A0
inputs can be actively driven by CMOS input signals or
tied to VCC or VSS.
INSTRUCTION BYTE (I[3:0])
The next byte sent to the X9271 contains the
instruction and register pointer information. The three
most significant bits are used to provide the instruction
operation code (I[3:0]). The RB and RA bits point to
one of the four Data Registers. P0 is the POT
selection; since the X9271 is single POT, P0 = 0. The
format is shown in Table 7.
REGISTER BANK SELECTION (R1, R0, P1, P0)
There are 16 registers organized into four banks.
Bank 0 is the default bank of registers. Only Bank 0
registers can be used for the data register to Wiper
Counter Register operations.
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations to the
TABLE 4. IDENTIFICATION BYTE FORMAT
DEVICE TYPE IDENTIFIER
SET TO 0 FOR
PROPER
OPERATION
INTERNAL
SLAVE
ADDRESS
ID3
ID2
ID1
ID0
0
A1
A0
01
(MSB)
(LSB)
TABLE 5. REGISTER SELECTION (DR0 TO DR3) TABLE
RB
RA
REGISTER
SELECTION
OPERATIONS
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
Data Register Read and Write; Wiper
Counter Register Operations
1
0
2
Data Register Read and Write; Wiper
Counter Register Operations
1
3
Data Register Read and Write; Wiper
Counter Register Operations
TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3)
P1
P0
BANK
SELECTION
OPERATIONS
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
Data Register Read and Write Only
1
0
2
Data Register Read and Write Only
1
3
Data Register Read and Write Only
TABLE 7. INSTRUCTION BYTE FORMAT
INSTRUCTION OPCODE
REGISTER
SELECTION
REGISTER BANK SELECTION FOR
SP1 REGISTER WRITE AND READ OPERATIONS)
POTENTIOMETER SELECTION
(WCR SELECTION) (Note 5)
I3
I2
I1
P0
RB
RA
P1
P0
(MSB)
(LSB)
NOTE:
5. Set to P0 = 0 for potentiometer operations.
X9271
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| X9271TXXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|PLASTIC |
| X9271TXXX-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|PLASTIC |
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